US3790961A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Random access dynamic semiconductor memory system
Assignee: Advanced Memory Systems Inc
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Filing: 1972-06-09
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Granted: 1974-02-05
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Expires: 1992-06-09
Abstract
Abstract A timing and priority assigning system for the automatic operation and refresh of a dynamic semiconductor memory operative with input-output signals characteristic of a magnetic core memory. A timing means is provided for the automatic execution of a read or write command for the semiconductor memory. A second timing system is provided which is initiated by a refresh oscillator so as to periodically and sequentially refresh a portion of the semiconductor memory. A counter is provided to retain the refresh address and to be advanced by a signal from the refresh oscillator. A means is also provided for automatically assigning priority to an externally received read or write command so as to reset a refresh cycle then in operation, or to prevent the initiation of a refresh cycle, until the execution of the command, whereby the refresh cycle is again automatically reinitiated upon the completion of the command.
Inventors
- 👤 T Palfi
- 👤 C Brooks
- 👤 G Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
219 words
A means for providing automatic operation of a dynamic semiconductor memory comprising: first means coupled to said memory and at least one read or write input line, which may have a command signal thereon, for generation of at least one timing signal for the execution of the command in said memory in response to said command signal; second means coupled to address input lines, a command signal line, and said memory for coupling an address to said memory upon the occurrence of said command signal; third means coupled to said memory for periodically initiating at least one timing signal for the refreshing of at least a portion of said memory; fourth means for counting coupled to and responsive to said third means; fifth means coupled to said third means, said fourth means and to said memory, said fifth means being responsive to said third means to sequentially address a portion of said memory for refreshing in accordance with the output of said fourth means; sixth means coupled to said third means and said memory initiated by said third means for the generation of at least one timing signal for the execution of a refresh operation; and seventh means coupled to said first means and said sixth means for resetting said sixth means during the operation of said first means.
Claim 2
Dependent Claim
219 words
A means for providing automatic operation of a dynamic semiconductor memory comprising: first means coupled to said memory and at least one read or write input line, which may have a command signal thereon, for generation of at least one timing signal for the execution of the command in said memory in response to said command signal; second means coupled to address input lines, a command signal line, and said memory for coupling an address to said memory upon the occurrence of said command signal; third means coupled to said memory for periodically initiating at least one timing signal for the refreshing of at least a portion of said memory; fourth means for counting coupled to and responsive to said third means; fifth means coupled to said third means, said fourth means and to said memory, said fifth means being responsive to said third means to sequentially address a portion of said memory for refreshing in accordance with the output of said fourth means; sixth means coupled to said third means and said memory initiated by said third means for the generation of at least one timing signal for the execution of a refresh operation; and seventh means coupled to said first means and said sixth means for resetting said sixth means during the operation of said first means.
Claim 3
Dependent Claim
35 words
The means of claim 1 further comprised of an eighth means coupled to said first means and said sixth means for preventing the initiation of said sixth means during the operation of said first means.
Claim 4
Dependent Claim
49 words
The means of claim 2 further comprised of nineth meAns coupled to said input line and said memory for gating read enable and write strobe signals to said memory in accordance with a command signal received on said input line and at a time determined by said first means.
Claim 5
Dependent Claim
208 words
A means for providing automatic operation of a dynamic semiconductor memory of the type requiring periodic refreshing, at least one timing signal to execute, read, write and refresh cycles, and memory command signals to execute read and write operations comprising: timing means coupled to at least one read or write input line, said timing means including a means for presenting said at least one timing signal upon receipt of a read or write signal, and a means for presenting at least one signal to effect refresh of an addressed portion of said memory upon receipt of a refresh initiate signal; addressing means for coupling an address to said memory initiated by said read or write signal; oscillator means for periodically providing a refresh initiate signal to said timing means; counter means coupled to said oscillator means for sequentially counting through all addresses required to refresh said memory; gate means for coupling said counter means output to said memory during the operation of said timing means initiated by said oscillator means; and reset means for interrupting and temporarily resetting said timing means as initiated by said oscillator means, upon receipt of a read or write signal, until said read or write operation has been substantially completed by said memory.
Claim 6
Dependent Claim
208 words
A means for providing automatic operation of a dynamic semiconductor memory of the type requiring periodic refreshing, at least one timing signal to execute, read, write and refresh cycles, and memory command signals to execute read and write operations comprising: timing means coupled to at least one read or write input line, said timing means including a means for presenting said at least one timing signal upon receipt of a read or write signal, and a means for presenting at least one signal to effect refresh of an addressed portion of said memory upon receipt of a refresh initiate signal; addressing means for coupling an address to said memory initiated by said read or write signal; oscillator means for periodically providing a refresh initiate signal to said timing means; counter means coupled to said oscillator means for sequentially counting through all addresses required to refresh said memory; gate means for coupling said counter means output to said memory during the operation of said timing means initiated by said oscillator means; and reset means for interrupting and temporarily resetting said timing means as initiated by said oscillator means, upon receipt of a read or write signal, until said read or write operation has been substantially completed by said memory.
Claim 7
Dependent Claim
42 words
The means of claim 4 wherein said timing means further includes a means for providing said memory command signals to said memory to execute a read or write operation, a predetermined time after the occurrence of said read or write signal, respectively.
Claim 8
Dependent Claim
224 words
For use with a dynamic memory system: a first timing means initiated by a read or a write signal for providing at least one timing signal useful in causing said memory to execute a read or a write command; first gate means for gating an address to said memory during the operation of said first timing means; a second timing means for providing at least one timing signal useful in refreshing said memory; an oscillator means; a bistable flip-flop means coupled to said oscillator means for setting by the output of said oscillator means and resetting by a reset signal; a second gate means for gating the output of said flip-flop means to said second timing means to initiate said second timing means, said second timing means further being coupled to said first timing means and being disabled during at least a substantial portion of the time of operation thereof; a counter means coupled to said flip-flop means for sequentially counting through a plurality of refresh addresses; a third gate means for gating the output of said counter means to said memory during the operation of said second timing means; and a reset means for resetting said second timing means upon initiation of said first timing means and reinitiating said timing means upon substantial completion of said timing signals from said first timing means.
Claim 9
Dependent Claim
224 words
For use with a dynamic memory system: a first timing means initiated by a read or a write signal for providing at least one timing signal useful in causing said memory to execute a read or a write command; first gate means for gating an address to said memory during the operation of said first timing means; a second timing means for providing at least one timing signal useful in refreshing said memory; an oscillator means; a bistable flip-flop means coupled to said oscillator means for setting by the output of said oscillator means and resetting by a reset signal; a second gate means for gating the output of said flip-flop means to said second timing means to initiate said second timing means, said second timing means further being coupled to said first timing means and being disabled during at least a substantial portion of the time of operation thereof; a counter means coupled to said flip-flop means for sequentially counting through a plurality of refresh addresses; a third gate means for gating the output of said counter means to said memory during the operation of said second timing means; and a reset means for resetting said second timing means upon initiation of said first timing means and reinitiating said timing means upon substantial completion of said timing signals from said first timing means.
Claim 10
Independent Claim
100 words
A method of operating a dynamic memory comprising: a. coupling an adddress to, and providing first timing signals to, said memory upon the occurrence of a read or write signal; b. providing a repetitive signal; c. advancing the count of a counter in response to said repetitive signal to sequentially count through a plurality of refresh address locations; d. initiating second timing signals responsive to said repetitive signal and coupling the output of the counter to the memory during said second timing signals; and e. inhibiting and resetting said second timing signals upon the occurrence of said first timing signals.
Claim 11
Independent Claim
100 words
A method of operating a dynamic memory comprising: a. coupling an adddress to, and providing first timing signals to, said memory upon the occurrence of a read or write signal; b. providing a repetitive signal; c. advancing the count of a counter in response to said repetitive signal to sequentially count through a plurality of refresh address locations; d. initiating second timing signals responsive to said repetitive signal and coupling the output of the counter to the memory during said second timing signals; and e. inhibiting and resetting said second timing signals upon the occurrence of said first timing signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-04 | 1977-08-06 | 1978-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-04 | 1981-08-06 | 1982-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-04 | 1985-08-06 | 1986-02-05 | $7700.00 | Window Closed / Lapsed |