Condenser memory circuit with regeneration means

Claim 2

A condenser memory circuit comprising: a condenser which stores information; a data terminal for supplying information which is to be stored and receiving information which is stored; an address instruction pulse-generating source which generates an address instruction pulse at writing-in and reading-out times; a first P-channel insulated-gate-field-effect transistor connected between said condenser and said data terminal which is turned on by said address instruction pulse and stores the information from said data terminal in said condenser at the writing-in times of the information and reads out to the data terminal the stored charge from said condenser at the readingout times of the information; a regenerative instruction pulse generating source for generating a regenerative instruction pulse which is at least synchronized with said address instruction pulse; an N-channel depletion mode insulated-gate-field-effect transistor rendered nonconducting when a stored charge is present in said condenser and connecting said regenerative instruction pulse-generating source to ground when said Nchannel depletion mode insulated-gate-field-effect transistor is rendered conducting; a regeneration voltage generating source whose voltage value substantially corresponds to the level of the information to be stored; and a second P-channel insulated-gate-field-effect transistor which is turned on in response to said regenerative instruction pulse only for the period in which said N-channel depletion mode insulated-gate-field-effect transistor is in the nonconducting stage and which connects said regeneration voltage generating source to said condenser.

Claim 3

A condenser memory circuit comprising: a condenser which stores information; a source for supplying information to be stored and receiving information which is stored; a pulse-generating source which generates an address instruction pulse at writing-in and reading-out times of the information; a first insulated-gate-field-effect transistor which is closed by said address instruction pulse and connects said information supply source to said condenser at the writing-in time of the information and reads out the stored charge from said condenser at the reading-out time of the information; a regenerative instruction pulse generating source for generating a regenerative instruction pulse which is at least synchronized with said address instruction pulse; a regeneration voltage-generating source whose voltage value substantially corresponds to said information to be stored; a second insulated-gate-field-effect transistor connected to said regenerative instruction pulse-generating source which is turned on by said regenerative instruction pulse; and a third insulated-gate-field-effect transistor connected between said condenser and regeneration voltage-generating source, said third insulated-gate-field-effect transIstor being turned on by said second insulated-gate-field-effect gate field effect transistor when both a charging voltage exists across said condenser and a regenerative instruction pulse is applied to said second insulated-gate-field-effect transistor.

Claim 4

A condenser memory circuit comprising: a condenser which stores information; a source for supplying information to be stored and receiving information which is stored; a pulse-generating source which generates an address instruction pulse at writing-in and reading-out times of the information; a first insulated-gate-field-effect transistor which is closed by said address instruction pulse and connects said information supply source to said condenser at the writing-in time of the information and reads out the stored charge from said condenser at the reading-out time of the information; a regenerative instruction pulse generating source for generating a regenerative instruction pulse which is at least synchronized with said address instruction pulse; a regeneration voltage-generating source whose voltage value substantially corresponds to said information to be stored; a second insulated-gate-field-effect transistor connected to said regenerative instruction pulse-generating source which is turned on by said regenerative instruction pulse; and a third insulated-gate-field-effect transistor connected between said condenser and regeneration voltage-generating source, said third insulated-gate-field-effect transIstor being turned on by said second insulated-gate-field-effect gate field effect transistor when both a charging voltage exists across said condenser and a regenerative instruction pulse is applied to said second insulated-gate-field-effect transistor.

Claim 5

A condenser memory circuit comprising: a first condenser which stores information as an electric charge; a data terminal for supplying information to be stored and receiving information which is stored; an address instruction pulse-generating source which generates an address instruction pulse at writing-in and reading-out times of the information; a first switching means which is closed by an address instruction pulse connecting said data terminal to said first condenser whereby said first condenser stores as an electric charge the information from said data terminal at writing-in time of the information and reads out the stored charge from said first condenser at reading-out time of the information; a regenerative instruction pulse generating source for generating a first regenerative instruction pulse which is at least synchronized with said address instruction pulse, and a second regenerative instruction pulse-generating source for generating a second regenerative instruction pulse which has a certain specific delay time relationship with said first regenerative instruction pulse; a second condenser which stores the same information as said first condenser; a regeneration voltage-generating source whose voltage value substantially corresponds to the information to be stored in said first condenser; a second switching means which is closed by said first regenerative instruction pulse and connects said first and second condensers in parallel with each other thereby effecting storage by said two condensers of the information from said information supply source; third switching means which is closed by said second regenerative instruction pulse and connects said first and second condensers in series with each other; and, fourth switching means closed through control of the voltage present due to said second condenser storing charge applied while said third switching means is closed, and said fourth switching means of which is closed in said manner when a stored charge is present in said first condenser and said second regenerative instruction pulse is applied thereto, and said fourth switching means of which connects said regeneration voltage generating source to said first condenser; and, said condenser memory circuit characterized in that the stored charge is regenerated at each arrival of said regenerative instruction pulse when a stored charge is present in said first condenser.

Claim 6

A condenser memory circuit comprising: a first condenser which stores information as an electric charge; a data terminal for supplying information to be stored and receiving information which is stored; an address instruction pulse-generating source which generates an address instruction pulse at writing-in and reading-out times of the information; a first switching means which is closed by an address instruction pulse connecting said data terminal to said first condenser whereby said first condenser stores as an electric charge the information from said data terminal at writing-in time of the information and reads out the stored charge from said first condenser at reading-out time of the information; a regenerative instruction pulse generating source for generating a first regenerative instruction pulse which is at least synchronized with said address instruction pulse, and a second regenerative instruction pulse-generating source for generating a second regenerative instruction pulse which has a certain specific delay time relationship with said first regenerative instruction pulse; a second condenser which stores the same information as said first condenser; a regeneration voltage-generating source whose voltage value substantially corresponds to the information to be stored in said first condenser; a second switching means which is closed by said first regenerative instruction pulse and connects said first and second condensers in parallel with each other thereby effecting storage by said two condensers of the information from said information supply source; third switching means which is closed by said second regenerative instruction pulse and connects said first and second condensers in series with each other; and, fourth switching means closed through control of the voltage present due to said second condenser storing charge applied while said third switching means is closed, and said fourth switching means of which is closed in said manner when a stored charge is present in said first condenser and said second regenerative instruction pulse is applied thereto, and said fourth switching means of which connects said regeneration voltage generating source to said first condenser; and, said condenser memory circuit characterized in that the stored charge is regenerated at each arrival of said regenerative instruction pulse when a stored charge is present in said first condenser.

Claim 7

A condenser memory circuit comprising: first and second condensers which store information; a source for supplying information to be stored and for receiving information which is stored; an address instruction pulse-generating source which generates an address instruction pulse at writing-in and reading-out times of the information; a first insulated-gate-field-effect transistor which is turned on by said address instruction pulse and connects said information supply source to said two condensers at the writing-in time of the information, and which reads out the stored charge from said first condenser at reading-out time of the information; a first regenerative instruction pulse generating source which is at least synchronized with said address instruction pulse; a second regenerative instruction pulse-generating source for generating a regenerative instruction pulse delayed a certain specific time behind said first regenerative instruction pulse; second and third insulated-gate-field-effect transistors which are turned on by said first regenerative instruction pulse and connect said two condensers in parallel with each other; a fourth insulated-gate-field-effect transistor which is turned on by said second regenerative instruction pulse and connects said tWo condensers in series with each other; and a fifth insulated-gate-field-effect transistor which is closed when a stored charge is present in said first condenser and said second regenerative instruction pulse is applied thereto, and which connects said regeneration voltage generating source to said first condenser.

Claim 8

A condenser memory circuit comprising: first and second condensers which store information; a source for supplying information to be stored and for receiving information which is stored; an address instruction pulse-generating source which generates an address instruction pulse at writing-in and reading-out times of the information; a first insulated-gate-field-effect transistor which is turned on by said address instruction pulse and connects said information supply source to said two condensers at the writing-in time of the information, and which reads out the stored charge from said first condenser at reading-out time of the information; a first regenerative instruction pulse generating source which is at least synchronized with said address instruction pulse; a second regenerative instruction pulse-generating source for generating a regenerative instruction pulse delayed a certain specific time behind said first regenerative instruction pulse; second and third insulated-gate-field-effect transistors which are turned on by said first regenerative instruction pulse and connect said two condensers in parallel with each other; a fourth insulated-gate-field-effect transistor which is turned on by said second regenerative instruction pulse and connects said tWo condensers in series with each other; and a fifth insulated-gate-field-effect transistor which is closed when a stored charge is present in said first condenser and said second regenerative instruction pulse is applied thereto, and which connects said regeneration voltage generating source to said first condenser.

Claim 9

A condenser memory circuit comprising: a condenser for storing information in the form of an electric charge; a first terminal for writing-in and reading-out information; a second terminal for providing address instruction pulses; a third terminal for providing a train of regenerative instruction pulses which is at least synchronized with the address instruction pulses; a regeneration power source for providing a voltage whose value substantially corresponds to the level of electric charge of the information; a first switch for connecting said condenser to said first terminal in response to application of the address instruction pulse to said first switch from said second terminal; and regeneration control means responsive to receipt of the regenerative instruction pulses from said third terminal for connecting said regeneration voltage generating source to said condenser only when a stored charge is present in said condenser.

Claim 10

A condenser memory circuit comprising: a condenser for storing information in the form of an electric charge; a first terminal for writing-in and reading-out information; a second terminal for providing address instruction pulses; a third terminal for providing a train of regenerative instruction pulses which is at least synchronized with the address instruction pulses; a regeneration power source for providing a voltage whose value substantially corresponds to the level of electric charge of the information; a first switch for connecting said condenser to said first terminal in response to application of the address instruction pulse to said first switch from said second terminal; and regeneration control means responsive to receipt of the regenerative instruction pulses from said third terminal for connecting said regeneration voltage generating source to said condenser only when a stored charge is present in said condenser.

Claim 11

A condenser memory circuit according to claim 5, wherein the regeneration control means comprise gating means for generating a gate output due to presence of the electric charge stored in said condenser when the regenerative instruction pulse is applied from said third terminal, and a second switch for connecting said regeneration power source to said condenser in response to application thereto of the gate output from said gating means.

Claim 12

A condenser memory circuit according to claim 6, wherein said gating means comprises a fourth switch which is closed by the regenerative instruction pulse, and means for applying the electric charge across said condenser to said second switch as the gate output when said fourth switch is closed.

Claim 13

A condenser memory circuit according to claim 7, wherein said first, second and fourth switches are insulated-gate-field-effect transistors of the same conductivity type.

Claim 14

A condenser memory circuit according to claim 6, wherein said gating means comprises a third switch which is opened by the electric charge stored in said condenser, and means applied with the regenerative instruction pulse from the third terminal for applying the regenerative instruction pulse to said second switch as the gate output when said third switch is opened.

Claim 15

A condenser memory circuit according to claim 9, wherein said second and third switches are insulated-gate-field-effect transistors of opposite conductivity type.

Claim 16

A condenser memory circuit according to claim 9, wherein said first and second switches are P-channel insulated-gate-field-effect transistors and said third switch is an N-channel depletion mode insulated-gate-field-effect transistor.