US3684897A
Expired / Lapsed
US
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Dynamic mos memory array timing system
Assignee: Cogar Corp
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Filing: 1970-08-19
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Granted: 1972-08-15
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Expires: 1990-08-19
Abstract
Abstract A dynamic MOS memory array timing system. If a mode signal is at a first (''''automatic mode'''') level, a refresh pulse is generated during every cycle defined by the system clock; if the mode signal is at a second (''''fast mode'''') level, a refresh pulse is generated only when a refresh input to the timing system is energized. Where speed is not of the utmost importance, the system can be operated in the automatic mode and there is no need to provide externally controlled refresh input signals. On the other hand, where speed is important, each system cycle can be speeded up by generating refresh signals only periodically; the increased speed is gained at the expense of the additional control circuits required to generate the refresh input signals. Thus the same timing system can be used in many different applications. The timing system utilizes delay elements for generating the many pulses necessary during each cycle. The delay elements are tapped so that fewer separate elements are required. To prevent loading of the delay elements, high-input impedance ECL circuits are used in the timing system. However, to make the system compatible with TTL inputs and outputs, various TTL-ECL and ECL-TTL converter circuits are used throughout the system.
Inventors
- 👤 Stanley R Anderson
- 👤 Richard W Bryant
- 👤 George K Tu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/406; G11C11/4067; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
46 words
A timing system for controlling refresh operations in a dynamic MOS memory cell array comprising means for generating refresh pulses for extension to said array, and means for selectively controlling the generation of said refresh pulses during every system cycle and during only selected syStem cycles.
Claim 2
Dependent Claim
46 words
A timing system for controlling refresh operations in a dynamic MOS memory cell array comprising means for generating refresh pulses for extension to said array, and means for selectively controlling the generation of said refresh pulses during every system cycle and during only selected syStem cycles.
Claim 3
Dependent Claim
64 words
A timing system in accordance with claim 1 further including means for detecting the mode in which said timing system should be operated, and means responsive to said detecting means for controlling a first mode of operation in which refresh pulses are generated during every system cycle and a second mode of operation in which refresh pulses are generated during only selected system cycles.
Claim 4
Dependent Claim
52 words
A timing system in accordance with claim 2 further including means for detecting when a refresh pulse should be generated while said system is operating in said second mode, and means responsive to the operation of said refresh pulse detecting means for identifying selected cycles in which refresh pulses should be generated.
Claim 5
Dependent Claim
45 words
A timing system for controlling refresh operations in a dynamic MOS memory cell array comprising means for generating refresh pulses for extension to said array, and means for selectively controlling the generation of said refresh pulses at a selected one of at least two rates.
Claim 6
Dependent Claim
45 words
A timing system for controlling refresh operations in a dynamic MOS memory cell array comprising means for generating refresh pulses for extension to said array, and means for selectively controlling the generation of said refresh pulses at a selected one of at least two rates.
Claim 7
Dependent Claim
63 words
A timing system in accordance with claim 4 further including means for detecting the mode in which said timing system should be operated, and means responsive to said detecting means for controlling a first mode of operation in which refresh pulses are generated at a first rate and a second mode of operation in which refresh pulses are generated at a second rate.
Claim 8
Dependent Claim
55 words
A timing system in accordance with claim 5 wherein said refresh pulse generating means is normally operative in said first mode for generating refresh pulses at a first rate, and further including means for detecting when refresh pulses should be generated at a second, slower rate while said system is operating in said second mode.
Claim 9
Dependent Claim
55 words
A timing system in accordance with claim 4 wherein said refresh pulse generating means is normally operative in a first mode for generating refresh pulses at a first rate, and further including means for detecting when refresh pulses should be generated at a second, slower rate while said system is operating in a second mode.
Claim 10
Dependent Claim
59 words
A timing system in accordance with claim 7 further including means for generating restore pulses for extension to said array during every data operation cycle, and means for causing said restore pulses to have a first duration in those cycles when refresh pulses are not generated and a second, longer duration in those cycles when refresh pulses are generated.
Claim 11
Dependent Claim
106 words
A timing system in accordance with claim 8 further including a plurality of input terminals, a plurality of output terminals for connection to said array, a first plurality of logic circuits connected to said input terminals for converting TTL input signal levels to ECL signal levels, a second plurality of logic circuits connected to said output terminals for converting ECL signal levels to TTL output levels, and a third plurality of logic circuits interconnecting said first and second pluralities of logic circuits, said third plurality of logic circuits including at leaSt one delay line having a tap thereon and a logic circuit connected to said tap.
Claim 12
Dependent Claim
59 words
A timing system in accordance with claim 4 further including means for generating restore pulses for extension to said array during every data operation cycle, and means for causing said restore pulses to have a first duration in those cycles when refresh pulses are not generated and a second, longer duration in those cycles when refresh pulses are generated.
Claim 13
Dependent Claim
107 words
A timing system in accordance with claim 10 further including a plurality of input terminals, a plurality of output terminals for connection to said array, a first plurality of logic circuits connected to said input terminals for converting TTL input signal levels to ECL signal levels, a second plurality of logic circuits connected to said output terminals for converting ECL signal levels to TTL output signal levels, and a third plurality of logic circuits interconnecting said first and second pluralities of logic circuits, said third Plurality of logic circuits including at least one delay line having a tap thereon and a logic circuit connected to said tap.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-15 | 1976-02-14 | 1976-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-15 | 1980-02-14 | 1980-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-15 | 1984-02-14 | 1984-08-15 | $7700.00 | Window Closed / Lapsed |