US7180165B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stackable electronic assembly
Assignee: Sanmina Corp
•
Filing: 2003-09-05
•
Granted: 2007-02-20
•
Expires: 2023-09-05
Abstract
Abstract On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.
Inventors
- 👤 Mark Ellsberry
- 👤 Charles E. Schmitz
- 👤 Chi She Chen
- 👤 Victor Allison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:58
CPC Classifications
H; H10; H10W; H10W90/00; H10W90/701; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/65; H10W72/00; H10W90/20; H10W90/22; H10W90/297; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
233 words
A chip-scale package comprising: a substrate having a first surface and an opposite second surface, the substrate composed of a controlled thermal expansion material; a memory die having a first surface and an opposite second surface, the first surface of the memory die mounted facing the first surface of the substrate, the memory die is electrically coupled to the substrate using a plurality of rigid underside coupling members, the substrate having a coefficient of expansion that matches a coefficient of expansion of the memory die to within six parts per million per degree Celsius or less, wherein the second surface of the memory die remains completely exposed; a plurality of solder balls mounted on the first surface of the substrate in a ball grid away configuration adjacent to the memory die, at least one of the solder balls electrically coupled to at least one of the underside coupling members; a plurality of pads coupled to the second surface of the substrate, each pad electrically coupled to one or more of the plurality of solder balls in a staggered routing scheme; and one or more electronic components mounted on the second surface of the substrate in an area opposite of the memory die, wherein the combined distance that an electronic component and the memory die protrude from the substrate is less than the distance that a solder ball and pad protrude from the substrate.
Claim 2
Dependent Claim
233 words
A chip-scale package comprising: a substrate having a first surface and an opposite second surface, the substrate composed of a controlled thermal expansion material; a memory die having a first surface and an opposite second surface, the first surface of the memory die mounted facing the first surface of the substrate, the memory die is electrically coupled to the substrate using a plurality of rigid underside coupling members, the substrate having a coefficient of expansion that matches a coefficient of expansion of the memory die to within six parts per million per degree Celsius or less, wherein the second surface of the memory die remains completely exposed; a plurality of solder balls mounted on the first surface of the substrate in a ball grid away configuration adjacent to the memory die, at least one of the solder balls electrically coupled to at least one of the underside coupling members; a plurality of pads coupled to the second surface of the substrate, each pad electrically coupled to one or more of the plurality of solder balls in a staggered routing scheme; and one or more electronic components mounted on the second surface of the substrate in an area opposite of the memory die, wherein the combined distance that an electronic component and the memory die protrude from the substrate is less than the distance that a solder ball and pad protrude from the substrate.
Claim 3
Dependent Claim
28 words
The chip-scale package of claim 1 further comprising: electrically conductive traces on the first surface to electrically couple at least one solder ball to the memory die directly.
Claim 4
Dependent Claim
21 words
The chip-scale package of claim 1 wherein the plurality of rigid underside coupling members are a second plurality of solder balls.
Claim 5
Dependent Claim
31 words
The chip-scale package of claim 1 wherein five sides of the memory die are completely exposed and the first surface of the memory device is substantially exposed for improved heat dissipation.
Claim 6
Dependent Claim
19 words
The chip-scale package of claim 1 wherein the memory die is made from a different material than the substrate.
Claim 7
Dependent Claim
195 words
A chip-scale package comprising: a substrate having a first surface and an opposite second surface; a semiconductor device mounted on the first surface of the substrate using a plurality of electrical conductors, the semiconductor device having a first surface and an opposite second surface, the first surface of the semiconductor device mounted facing the first surface of the substrate, wherein the second surface of the memory device remains completely exposed for improved ventilation; a plurality of solder balls mounted on the first surface of the substrate in a ball grid away configuration adjacent to the semiconductor device, at least one of the solder balls electrically coupled to the semiconductor device; and a plurality of pads coupled to the second surface of the substrate, each pad electrically coupled to one or more of the plurality of solder balls in a staggered routing scheme which, when a plurality of chip-scale packages are stacked together, causes a solder ball of a first chip-scale package to be uniquely electrically coupled with an electrical conductor of a semiconductor device mounted on a second chip-scale package N levels from the first chip-scale package, where N is an integer greater than two.
Claim 8
Dependent Claim
195 words
A chip-scale package comprising: a substrate having a first surface and an opposite second surface; a semiconductor device mounted on the first surface of the substrate using a plurality of electrical conductors, the semiconductor device having a first surface and an opposite second surface, the first surface of the semiconductor device mounted facing the first surface of the substrate, wherein the second surface of the memory device remains completely exposed for improved ventilation; a plurality of solder balls mounted on the first surface of the substrate in a ball grid away configuration adjacent to the semiconductor device, at least one of the solder balls electrically coupled to the semiconductor device; and a plurality of pads coupled to the second surface of the substrate, each pad electrically coupled to one or more of the plurality of solder balls in a staggered routing scheme which, when a plurality of chip-scale packages are stacked together, causes a solder ball of a first chip-scale package to be uniquely electrically coupled with an electrical conductor of a semiconductor device mounted on a second chip-scale package N levels from the first chip-scale package, where N is an integer greater than two.
Claim 9
Dependent Claim
30 words
The chip-scale package of claim 6 further comprising: one or more electrical components mounted on the second surface of the substrate in an area substantially opposite of the semiconductor device.
Claim 10
Dependent Claim
39 words
The chip-scale package of claim 7 wherein the combined distance that one or more electrical components and the semiconductor device protrude from the substrate is less than the distance that a solder ball and pad protrude from the substrate.
Claim 11
Dependent Claim
41 words
The chip-scale package of claim 6 wherein the substrate includes a controlled thermal expansion material with a coefficient of expansion that matches the coefficient of expansion of the semiconductor device to within six parts per million per degree Celsius or less.
Claim 12
Dependent Claim
27 words
The chip-scale package of claim 6 further comprising: electrically conductive traces on the first surface to directly couple at least one solder ball to the semiconductor device.
Claim 13
Dependent Claim
19 words
The chip-scale package of claim 6 wherein the memory device is made from a different material than the substrate.
Claim 14
Dependent Claim
171 words
A stackable electronic assembly comprising: a plurality of chip-scale packages, the plurality of chip-scale packages arranged in a stacked configuration, each chip-scale package including a substrate having a first surface and an opposite second surface, the substrate composed of a controlled thermal expansion material; a semiconductor device coupled to traces on the first surface of the substrate using underside coupling members; a plurality of solder balls mounted on the first surface of the substrate in a ball grid away configuration adjacent to the semiconductor device, at least one of the solder balls electrically coupled to the semiconductor device; and a plurality of pads coupled to the second surface of the substrate, each pad electrically coupled to one or more of the plurality of solder balls in a staggered routing scheme, wherein all chip-scale packages in the stacked configuration have identical routing traces, and the substrate having a coefficient of expansion that matches a coefficient of expansion of the semiconductor device to within six parts per million per degree Celsius or less.
Claim 15
Dependent Claim
171 words
A stackable electronic assembly comprising: a plurality of chip-scale packages, the plurality of chip-scale packages arranged in a stacked configuration, each chip-scale package including a substrate having a first surface and an opposite second surface, the substrate composed of a controlled thermal expansion material; a semiconductor device coupled to traces on the first surface of the substrate using underside coupling members; a plurality of solder balls mounted on the first surface of the substrate in a ball grid away configuration adjacent to the semiconductor device, at least one of the solder balls electrically coupled to the semiconductor device; and a plurality of pads coupled to the second surface of the substrate, each pad electrically coupled to one or more of the plurality of solder balls in a staggered routing scheme, wherein all chip-scale packages in the stacked configuration have identical routing traces, and the substrate having a coefficient of expansion that matches a coefficient of expansion of the semiconductor device to within six parts per million per degree Celsius or less.
Claim 16
Dependent Claim
49 words
The stackable electronic assembly of claim 12 , the semiconductor device having a first surface and an opposite second surface, the first surface of the semiconductor device mounted towards the first surface of the substrate, wherein the second surface of the semiconductor device remains completely exposed for improved ventilation.
Claim 17
Dependent Claim
31 words
The stackable electronic assembly of claim 13 wherein five sides of the semiconductor device are completely exposed and the first surface of the memory device is exposed for improved heat dissipation.
Claim 18
Dependent Claim
61 words
The stackable electronic assembly of claim 12 further comprising: one or more electrical components mounted on the second surface of the substrate in an area opposite of the semiconductor device, wherein the combined distance that an electronic component and the semiconductor device protrude from the substrate is less than the distance that a solder ball and pad protrude from the substrate.
Claim 19
Dependent Claim
20 words
The stackable electronic assembly of claim 12 wherein the semiconductor device is made from a different material than the substrate.
Claim 20
Dependent Claim
213 words
A memory module comprising: a main substrate with an interface to couple the memory module to other devices; and one or more stacks of memory devices coupled to a first surface of the main substrate, at least one stack of memory devices including a plurality of chip-scale packages, the plurality of chip-scale packages arranged in a stack, all chip-scale packages in the stack having identical routing traces at every level of the stack which facilitates a staggered routing scheme between the chip-scale packages, each chip-scale package including a substrate having a first surface and an opposite second surface, a memory semiconductor die electrically coupled to traces on the first surface of the substrate, and a plurality of solder balls mounted on the first surface of the substrate adjacent to the memory semiconductor die, at least one of the solder balls electrically coupled to the memory semiconductor die, wherein the substrate is composed of a controlled thermal expansion material, the substrate has a coefficient of expansion that matches a coefficient of expansion of the memory semiconductor die to within six parts per million per degree Celsius or less, and five sides of the memory semiconductor die are completely exposed and a sixth side of the memory semiconductor die is exposed for improved heat dissipation.
Claim 21
Dependent Claim
213 words
A memory module comprising: a main substrate with an interface to couple the memory module to other devices; and one or more stacks of memory devices coupled to a first surface of the main substrate, at least one stack of memory devices including a plurality of chip-scale packages, the plurality of chip-scale packages arranged in a stack, all chip-scale packages in the stack having identical routing traces at every level of the stack which facilitates a staggered routing scheme between the chip-scale packages, each chip-scale package including a substrate having a first surface and an opposite second surface, a memory semiconductor die electrically coupled to traces on the first surface of the substrate, and a plurality of solder balls mounted on the first surface of the substrate adjacent to the memory semiconductor die, at least one of the solder balls electrically coupled to the memory semiconductor die, wherein the substrate is composed of a controlled thermal expansion material, the substrate has a coefficient of expansion that matches a coefficient of expansion of the memory semiconductor die to within six parts per million per degree Celsius or less, and five sides of the memory semiconductor die are completely exposed and a sixth side of the memory semiconductor die is exposed for improved heat dissipation.
Claim 22
Dependent Claim
16 words
The memory module of claim 17 wherein the memory module is a dual inline memory module.
Claim 23
Dependent Claim
24 words
The memory module of claim 17 further comprising: one or more stacks of memory devices coupled to a second surface of the main substrate.
Claim 24
Dependent Claim
48 words
The memory module of claim 17 wherein the coefficient of expansion of the main substrate is greater than the coefficient of expansion of the chip-scale package substrate, the coefficient of expansion of the chip-scale package substrate is greater than the coefficient of expansion of the memory semiconductor die.
Claim 25
Dependent Claim
68 words
The memory module of claim 17 wherein the coefficient of expansion of the chip-scale package substrate is selected such that the differential between a first interface thermal stress from the main substrate to a chip-scale package and a second interface thermal stress from the chip-scale package to the memory die is minimized so that the structural integrity of electrical joints at the first and second interfaces are retained.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-02-19 | 2010-08-21 | 2011-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-02-19 | 2014-08-21 | 2015-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-02-19 | 2018-08-21 | 2019-02-20 | $7700.00 | Window Closed / Lapsed |