Stackable modules and multimodular assemblies

Claim 2

A stacked, resealable, multimodular, electronic circuit assembly comprising: (1) at least two stacked modules, each module comprising a dielectric substrate having upper and lower planar surfaces and at least one cavity in at least one of said surfaces said cavity having lesser width and breadth than said one surface, thereby forming a dielectric substrate matrix surround said cavity; (2) at least one electronic component comprising a three-dimensional stack of IC chips positioned within at least one cavity of each of the said modules and having I/O contacts; (3) a closure plate overlying said cavity, enclosing same and bonded to said one surface to provide a hermetic seal of said cavity; (4) a plurality of electrically conductive through-vias between said upper and lower planar surfaces of each of said modules outside of said cavity and within said matrix, each of said through-vias having exposed electric contact points where it penetrates said upper and lower planar surfaces; (5) said I/O contacts of said electronic components in each of said modules being electrically connected with through-vias in each respective module; and (6) a planar, multichannel connector between each opposing pair of said modules for sealing said modules when pressed together and having separate electrically conductive through channels in an array on centers of 0.2 inch or less and electrically coupling opposing through-vias in said adjacent modules.

Claim 3

The assembly defined in claim 1, wherein said modules comprise multiple, laminated, dielectric lamina oriented in planes generally perpendicular to the major axis of said through-vias.

Claim 4

The assembly defined in claim 2, wherein said layers of dielectric lamina comprise a refractory inorganic oxide, nitride, carbide, or combination thereof.

Claim 5

The assembly defined in claim 2, wherein said I/O contacts are connected to said through-vias by electrically conductive paths along the interfaces between adjacent layers.

Claim 6

The assembly defined in claim 4, comprising at least two rows of said through-vias bordering at least one side of said cavities in said modules, and the number of interfaces between said layers in at least one of said modules is at least equal to the number of said rows of said through-vias.

Claim 7

The multimodular assembly defined in claim 5, wherein said electronic components within said assembly, combined, have at least about 50 of said I/O contacts electrically connected to said through-vias, and each of said modules has at least about 50 of said through-vias electrically connected with corresponding opposing vias on adjacent modules.

Claim 8

The assembly defined in claim 4, comprising at least four rows of said through-vias bordering to at least one side of the cavities in said modules and at least about five layers of lamina in at least one of said modules forming interfaces available for forming conductive paths between said I/O contacts and said through-vias.

Claim 9

The multimodular assembly defined in claim 4, comprising at least three of said stacked modules, at least about 50 of said through-vias, and at least about 50 I/O contacts on said components connected to said vias.

Claim 10

The multimodular assembly defined in claim 2, wherein said I/O contacts are interconnected with said through-vias in a pattern such that each of said components can be tested by determining electrical signals in said through-vias.

Claim 11

The stacked, multimodular assembly defined in claim 2, further comprising a number of said through-vias in excess of that required for connection with said I/O contacts on said components such that said assembly comprises unconnected through-vias.

Claim 12

The multimodular assembly defined in claim 10, comprising at least one memory IC chip.

Claim 13

An expandable memory, stacked, multimodular assembly comprising the assembly defined in claim 10 having memory and processor logic circuitry.

Claim 14

The assembly defined in claim 1, wherein said multichannel connector array comprises a dielectric plastic or elastomeric layer comprising said electrically conductive channels.

Claim 15

The assembly defined in claim 13, wherein each of said channels comprises an aperture through said layer containing a compressible electrically conductive wire bundle.

Claim 16

The assembly defined in claim 5, wherein said compressible wire bundle comprises a randomly wound wire strand.

Claim 17

A stacked, resealable, multimodular, electronic circuit assembly comprising: (1) at least two stacked modules, each module comprising a dielectric substrate formed of multiple, dielectric lamina having upper and lower planar surfaces forming interfaces between adjacent lamina, and at least one cavity in at least one of said surfaces, said cavity having lesser width and breadth than said one surface, thereby forming a dielectric substrate matrix surrounding said cavity; (2) a plurality of electrically conductive through-vias oriented along axes generally perpendicular to the planar surfaces of said lamina and arrayed in at least two rows of said through-vias bordering at least one side of said cavities in said modules, and the number of interfaces between said layers in at least one of said modules is at least equal to the number of said rows of said through-vias between said upper and lower planar surfaces of each of said modules outside of said cavity and within said matrix, each of said through-vias having exposed electric contact points where it penetrates said upper and lower planar surfaces; (3) at least one electronic component comprising a three-dimensional stack of IC chips positioned within at least one cavity of each of the said modules and having I/O contacts connected to said through-vias by electrically conductive paths along the interfaces between adjacent layers; (4) a closure plate overlying said cavity, enclosing same and bonded to said one surface to provide a hermetic seal of said cavity; (5) at least about 50 of said I/O contacts electrically connected to said through-vias, and each of said modules has at least about 50 of said through-vias electrically connected with corresponding opposing vias on adjacent modules with said I/O contacts of said electronic components in each of said modules being electrically connected with through-vias in each respective module; (6) a planar, multichannel connector array between each opposing pair of said modules having separate electrically conductive channels electrically coupling opposing through-vias in said adjacent modules and for sealing said modules when pressed together; and (7) contact pads at either end of said through-vias having a diameter greater than the maximum diameter of the through-vias, with said through-vias arranged in a grid pattern on centers of about 0.2 inch or less, and each having a diameter within the module matrix of about 0.05 inch or less.

Claim 18

A stacked, resealable, multimodular, electronic circuit assembly comprising: (1) at least two stacked modules, each module comprising a dielectric substrate formed of multiple, dielectric lamina having upper and lower planar surfaces forming interfaces between adjacent lamina, and at least one cavity in at least one of said surfaces, said cavity having lesser width and breadth than said one surface, thereby forming a dielectric substrate matrix surrounding said cavity; (2) a plurality of electrically conductive through-vias oriented along axes generally perpendicular to the planar surfaces of said lamina and arrayed in at least two rows of said through-vias bordering at least one side of said cavities in said modules, and the number of interfaces between said layers in at least one of said modules is at least equal to the number of said rows of said through-vias between said upper and lower planar surfaces of each of said modules outside of said cavity and within said matrix, each of said through-vias having exposed electric contact points where it penetrates said upper and lower planar surfaces; (3) at least one electronic component comprising a three-dimensional stack of IC chips positioned within at least one cavity of each of the said modules and having I/O contacts connected to said through-vias by electrically conductive paths along the interfaces between adjacent layers; (4) a closure plate overlying said cavity, enclosing same and bonded to said one surface to provide a hermetic seal of said cavity; (5) at least about 50 of said I/O contacts electrically connected to said through-vias, and each of said modules has at least about 50 of said through-vias electrically connected with corresponding opposing vias on adjacent modules with said I/O contacts of said electronic components in each of said modules being electrically connected with through-vias in each respective module; (6) a planar, multichannel connector array between each opposing pair of said modules having separate electrically conductive channels electrically coupling opposing through-vias in said adjacent modules and for sealing said modules when pressed together; and (7) contact pads at either end of said through-vias having a diameter greater than the maximum diameter of the through-vias, with said through-vias arranged in a grid pattern on centers of about 0.2 inch or less, and each having a diameter within the module matrix of about 0.05 inch or less.

Claim 19

A stackable module for containing and interconnecting electronic components comprising a dielectric substrate having upper and lower planar surfaces and at least one cavity on at least one of said surfaces for containing one or more three-dimensional IC chip stacks, said substrate comprising multiple, laminated layers of said dielectric, at least 100 electrically conductive through-vias between said upper and lower planar surfaces of said module outside of said cavity and within the matrix of said module in a grid pattern bordering said cavity and being spaced on centers of about 0.2 inch or less and having maximum diameters within the matrix of said module of about 0.05 inch or less, each of said through-vias having exposed electric contacts at either end where it penetrates said upper and lower surfaces of said planar substrate and electrically conductive signal paths interconnecting said through-vias and the interior of said cavity and being located between said layers of said module for communicating electronic signals to and from electronic components within said cavity, and a closure plate covering said cavity and sealed thereabout to hermetically contain said cavity.

Claim 20

A stackable module for containing and interconnecting electronic components comprising a dielectric substrate having upper and lower planar surfaces and at least one cavity on at least one of said surfaces for containing one or more three-dimensional IC chip stacks, said substrate comprising multiple, laminated layers of said dielectric, at least 100 electrically conductive through-vias between said upper and lower planar surfaces of said module outside of said cavity and within the matrix of said module in a grid pattern bordering said cavity and being spaced on centers of about 0.2 inch or less and having maximum diameters within the matrix of said module of about 0.05 inch or less, each of said through-vias having exposed electric contacts at either end where it penetrates said upper and lower surfaces of said planar substrate and electrically conductive signal paths interconnecting said through-vias and the interior of said cavity and being located between said layers of said module for communicating electronic signals to and from electronic components within said cavity, and a closure plate covering said cavity and sealed thereabout to hermetically contain said cavity.

Claim 21

The stackable module defined in claim 17, comprising at least three of said laminated layers and having said electrically conductive pathways between at least two of said layers interconnecting said through-vias and said cavity.

Claim 22

A multimodular assembly comprising at least two stacked modules defined in claim 17, each containing at least one electronic component and at least one of said modules containing said three-dimensional stack of IC chips, the I/O contacts of said electronic components being interconnected with said through-vias via said inter laminar electronic signal paths, each of said modules being electrically interconnected with at least one adjacent module through a resealable, multichannel connector array having separate electrically conductive channels electrically coupling each pair of opposing, matching through-vias in said adjacent modules and for sealing said modules.

Claim 23

A stacked, resealable, multimodular, electronic circuit assembly comprising at least three stacked modules, each module comprising multiple laminated dielectric lamina layers of a refractory inorganic oxide forming a dielectric substrate having upper and lower planar surfaces and at least one cavity in at least one surface of each of said modules for containing at least one electronic component; a. said laminated dielectric lamina being oriented in planes generally parallel to said upper and lower planar surfaces; b. at least one three-dimensional chip stack of electronic components positioned within at least one cavity on each of said modules and having I/O contacts; c. at least about 200 electrically conductive through-vias between said upper and lower planar surfaces of each of said modules through the matrix thereof outside of said cavity and within the outer surface of each module, each of said through-vias having exposed electrical contact points where it penetrates said upper and lower planar surfaces of said module, and the position of said contact points on each surface of said module corresponding to the position of corresponding through-via contact points on adjacent modules, whereby said contact points can be electrically interconnected as described hereinafter; d. at least about 100 of said I/O contacts of said electronic components being electrically connected to said through-vias by electrically conductive paths along the interfaces between adjacent layers of said dielectric lamina; and e. a resealable, multichannel connector array between each opposing pair of said modules having separate electrically conductive channels electrically coupling opposing, matching through-vias in said adjacent modules and for sealing said modules when pressed together, thereby hermetically sealing each of said cavities, said multichannel connector array comprising a dielectric plastic or elastomeric layer with said electrically conductive channels in an array on centers of about 0.2 inch or less.

Claim 24

A stacked, resealable, multimodular, electronic circuit assembly comprising at least three stacked modules, each module comprising multiple laminated dielectric lamina layers of a refractory inorganic oxide forming a dielectric substrate having upper and lower planar surfaces and at least one cavity in at least one surface of each of said modules for containing at least one electronic component; a. said laminated dielectric lamina being oriented in planes generally parallel to said upper and lower planar surfaces; b. at least one three-dimensional chip stack of electronic components positioned within at least one cavity on each of said modules and having I/O contacts; c. at least about 200 electrically conductive through-vias between said upper and lower planar surfaces of each of said modules through the matrix thereof outside of said cavity and within the outer surface of each module, each of said through-vias having exposed electrical contact points where it penetrates said upper and lower planar surfaces of said module, and the position of said contact points on each surface of said module corresponding to the position of corresponding through-via contact points on adjacent modules, whereby said contact points can be electrically interconnected as described hereinafter; d. at least about 100 of said I/O contacts of said electronic components being electrically connected to said through-vias by electrically conductive paths along the interfaces between adjacent layers of said dielectric lamina; and e. a resealable, multichannel connector array between each opposing pair of said modules having separate electrically conductive channels electrically coupling opposing, matching through-vias in said adjacent modules and for sealing said modules when pressed together, thereby hermetically sealing each of said cavities, said multichannel connector array comprising a dielectric plastic or elastomeric layer with said electrically conductive channels in an array on centers of about 0.2 inch or less.

Claim 25

The multimodular assembly defined in claim 20, wherein each of said channels in said connector array comprises an aperture through said layer containing a compressible, electrically conductive wire bundle.

Claim 26

The stacked, multimodular assembly defined in claim 20, wherein said through-vias constitute continuous thermal conductive paths through said assembly.

Claim 27

A method for assembling and electrically interconnecting electronic components which comprises positioning at least one three-dimensional IC chip array in said cavities of each of at least 2 of said modules defined in claim 17, closing and hermetically sealing each of said cavities with a closure plate to form hermetically sealed modules, and electrically connecting the I/O contacts of each said IC chip array to said conductive through-vias, stacking said modules and electrically interconnecting said through-vias therein by interposing between each adjacent pair of modules a multichannel connector array comprising a compressible, dielectric layer having electrically conductive channels corresponding to and interconnecting each opposing pair of through-vias in adjacent modules when pressed together; said through-vias and electrically conductive channels in said connector array being spaced on centers of about 0.2 inch or less.

Claim 28

The method of claim 23 which comprises using a dielectric plastic or elastomeric layer as said multichannel connector array.