Semiconductor device including memory unit and semiconductor module including memory units

Claim 2

A semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit which includes a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned to the memory unit and the memory unit selecting signal, and an identifier generating circuit, wherein the identifier generating circuit is an adder circuit for carrying the identifier of the memory unit by a half bit and generating identifiers for other memory units.

Claim 3

The semiconductor device of claim 1 , wherein the identifier is one bit data or a plurality of bit data.

Claim 4

The semiconductor device of claim 1 , wherein the identifier generating circuit is electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply, and the standard voltage power supply voltage or the circuit operation power supply is used as the identifier.

Claim 5

The semiconductor device of claim 1 , wherein the memory unit selecting circuit is a comparator for comparing the identifier with the memory unit selecting signal.

Claim 6

The semiconductor device of claim 1 , wherein the memory unit is either a DRAM or a SRAM.

Claim 7

The semiconductor device of claim 1 , wherein the memory unit is a non-volatile memory which is ROM, EPROM, or EEPROM.

Claim 8

The semiconductor device of claim 1 , wherein the selecting signal terminal which receives the memory unit selecting signal is a surplus signal terminal out of address signal terminals which are used for selecting address of the memory unit.

Claim 9

A semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit which is provided outside the memory unit and includes a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and a memory unit selecting signal, and an identifier generating circuit, wherein the identifier generating circuit is an adder circuit for carrying the identifier of the memory unit by a half bit and generating identifiers for other memory units.

Claim 10

A semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit which is provided outside the memory unit and includes a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and a memory unit selecting signal, and an identifier generating circuit, wherein the identifier generating circuit is an adder circuit for carrying the identifier of the memory unit by a half bit and generating identifiers for other memory units.

Claim 11

The semiconductor device of claim 8 , wherein the memory unit and the identifying unit are constituted by separate semiconductor chips.

Claim 12

The semiconductor device of claim 9 , wherein the semiconductor chips constituting the memory unit and the identifying unit are constituted by separate packages.

Claim 13

The semiconductor device of claim 9 , wherein the semiconductor chips constituting the memory unit and the identifying unit are constituted by the same package.

Claim 14

The semiconductor device of claim 9 , wherein the selecting signal terminal is provided in the semiconductor chip constituting the identifying unit.

Claim 15

A semiconductor module comprising: a first memory unit; a second memory unit positioned on or by the first memory unit; a first selecting signal terminal provided in the first memory unit and for receiving a memory unit selecting signal which is common to a plurality of memory units; a second selecting signal terminal provided in the second memory unit and for receiving the memory unit selecting signal which is common to a plurality of memory units; a first identifying unit including: a first memory unit selecting circuit for selecting the first memory unit on the basis of a first identifier assigned thereto and the memory unit selection signal; and a first identifier generating circuit, wherein the first identifier generating circuit is a first adder circuit for carrying the first identifier of the first memory unit by a half bit and generating a second identifier for the second memory unit; and a second identifying unit including: a second memory unit selecting circuit for selecting the second memory unit on the basis of the second identifier assigned thereto and the memory unit selection signal; and a second identifier generating circuit, wherein the second identifier generating circuit is a second adder circuit for carrying the second identifier of the second memory unit by a half bit and generating a third identifier for a third memory unit.

Claim 16

A semiconductor module comprising: a first memory unit; a second memory unit positioned on or by the first memory unit; a first selecting signal terminal provided in the first memory unit and for receiving a memory unit selecting signal which is common to a plurality of memory units; a second selecting signal terminal provided in the second memory unit and for receiving the memory unit selecting signal which is common to a plurality of memory units; a first identifying unit including: a first memory unit selecting circuit for selecting the first memory unit on the basis of a first identifier assigned thereto and the memory unit selection signal; and a first identifier generating circuit, wherein the first identifier generating circuit is a first adder circuit for carrying the first identifier of the first memory unit by a half bit and generating a second identifier for the second memory unit; and a second identifying unit including: a second memory unit selecting circuit for selecting the second memory unit on the basis of the second identifier assigned thereto and the memory unit selection signal; and a second identifier generating circuit, wherein the second identifier generating circuit is a second adder circuit for carrying the second identifier of the second memory unit by a half bit and generating a third identifier for a third memory unit.

Claim 17

The semiconductor module of claim 13 , wherein the first identifier generating circuit is electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply, and the standard voltage power supply or the circuit operation power supply is used as the first identifier.

Claim 18

The semiconductor module of claim 13 , wherein the first memory unit selecting circuit is a comparator for comparing the first identifier and the memory unit selecting signal, and the second memory unit selecting circuit is a comparator for comparing the second identifier and the memory unit selecting signal.

Claim 19

The semiconductor module of claim 13 , wherein the second memory unit is stacked on the first memory unit.

Claim 20

The semiconductor module of claim 13 , wherein the second memory unit is juxtaposed to the first memory unit.

Claim 21

The semiconductor module of claim 13 further comprising at least one memory unit and at least one identifying unit.

Claim 22

A semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit including an identifier generating circuit provided with a fuse element and a resistor element, wherein the resistor element has a resistance value which is higher than a resistance value of the fuse element for generating an identifier assigned to the memory unit, and a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and the memory unit selecting signal.

Claim 23

A semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit including an identifier generating circuit provided with a fuse element and a resistor element, wherein the resistor element has a resistance value which is higher than a resistance value of the fuse element for generating an identifier assigned to the memory unit, and a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and the memory unit selecting signal.

Claim 24

The semiconductor device of claim 19 , wherein: the fuse element has one end thereof electrically connected to a standard voltage power supply for a circuit system and the other end thereof electrically connected to the memory unit selecting circuit and one end of the resistance element; and the resistance element has the other end thereof electrically connected to the circuit operation power supply for the circuit system.