US5796653A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for the selection of redundant memory elements and flash EEPROM memory comprising said circuit
Assignee: STMicroelectronics SA
•
Filing: 1995-02-22
•
Granted: 1998-08-18
•
Expires: 2015-02-22
Abstract
Abstract In order to carry out the automatic selection of redundant memory elements (rows or columns) to replace defective elements, the addresses of the elements to be replaced are compared with the current address. In order to improve the reliability by reducing the number of non-volatile memory cells normally containing the addresses of the elements to be replaced, the selection circuit has means to compute certain of these addresses from an actually stored address. Application notably to FLASH EEPROMs.
Inventors
- 👤 Jean-Marie Gaultier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/78; G11C29/785; G11C29/789; G11C29/80; G11C29/804; G11C29/816; G11C29/82
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
217 words
An integrated circuit memory, comprising: an array of FLASH EEPROM memory cells, organized in rows and columns; a plurality of redundant portions, each parallel to rows or columns of said array; a nonvolatile memory storing defective address identifiers; row and column selection logic, connected to access one of said rows and one of said columns as selected by externally received address bits, to thereby select one or more of said memory cells; and redundancy selection logic, connected to said nonvolatile memory storing defective address identifiers, selectably operable in two modes; wherein, in a first mode, said redundancy selection logic, whenever the externally received address bits match one of said defective address identifiers in said nonvolatile memory, inactivates a portion of said array whose address corresponds to said defective address identifier, and also activates one of said redundant portions; wherein, in said first mode, said redundancy selection logic, whenever the externally received address bits match one of said defective address identifiers in said nonvolatile memory plus a predetermined increment value, inactivates a portion of said array whose address matches said defective address identifier plus said predetermined increment value, and also activates one of said redundant portions; wherein, in a second mode, said redundancy selection logic activates two topologically adjacent ones of said redundant portions for each accessed address.
Claim 2
Dependent Claim
217 words
An integrated circuit memory, comprising: an array of FLASH EEPROM memory cells, organized in rows and columns; a plurality of redundant portions, each parallel to rows or columns of said array; a nonvolatile memory storing defective address identifiers; row and column selection logic, connected to access one of said rows and one of said columns as selected by externally received address bits, to thereby select one or more of said memory cells; and redundancy selection logic, connected to said nonvolatile memory storing defective address identifiers, selectably operable in two modes; wherein, in a first mode, said redundancy selection logic, whenever the externally received address bits match one of said defective address identifiers in said nonvolatile memory, inactivates a portion of said array whose address corresponds to said defective address identifier, and also activates one of said redundant portions; wherein, in said first mode, said redundancy selection logic, whenever the externally received address bits match one of said defective address identifiers in said nonvolatile memory plus a predetermined increment value, inactivates a portion of said array whose address matches said defective address identifier plus said predetermined increment value, and also activates one of said redundant portions; wherein, in a second mode, said redundancy selection logic activates two topologically adjacent ones of said redundant portions for each accessed address.
Claim 3
Dependent Claim
21 words
An integrated circuit memory as in claim 1, wherein said array of memory cells comprises at least 16 megabits of memory.
Claim 4
Dependent Claim
15 words
An integrated circuit memory as in claim 1, wherein said predetermined increment value is 2.
Claim 5
Dependent Claim
22 words
An integrated circuit memory as in claim 1, wherein said predetermined increment value corresponds to the address difference between topologically adjacent elements.
Claim 6
Independent Claim
234 words
A method of operating an integrated circuit memory, comprising the steps of a) providing an integrated circuit memory comprising an array of FLASH EEPROM memory cells, organized in rows and columns, a plurality of redundant portions, each parallel to rows or columns of said array, a nonvolatile memory storing defective address identifiers, row and column selection logic, connected to access one of said rows and one of said columns as selected by externally received address bits, to thereby select one or more of said memory cells, and redundancy selection logic, connected to said nonvolatile memory storing defective address identifiers, said redundancy selection logic being operable in two modes; b) in a first mode, i) when the externally received address bits match one of said defective address identifiers in said nonvolatile memory, inactivating a portion of said array whose address corresponds to said defective address identifier, and also activates one of said redundant portions; ii) when the externally received address bits match one of said defective address identifiers in said nonvolatile memory plus a predetermined increment value, inactivates a portion of said array whose address matches said defective address identifier plus said predetermined increment value, and also activates one of said redundant portions, and c) in a second mode, when the externally received address bits match one of said defective address identifiers in said non-volatile memory, activating two topologically adjacent ones of said redundant portions.
Claim 7
Independent Claim
234 words
A method of operating an integrated circuit memory, comprising the steps of a) providing an integrated circuit memory comprising an array of FLASH EEPROM memory cells, organized in rows and columns, a plurality of redundant portions, each parallel to rows or columns of said array, a nonvolatile memory storing defective address identifiers, row and column selection logic, connected to access one of said rows and one of said columns as selected by externally received address bits, to thereby select one or more of said memory cells, and redundancy selection logic, connected to said nonvolatile memory storing defective address identifiers, said redundancy selection logic being operable in two modes; b) in a first mode, i) when the externally received address bits match one of said defective address identifiers in said nonvolatile memory, inactivating a portion of said array whose address corresponds to said defective address identifier, and also activates one of said redundant portions; ii) when the externally received address bits match one of said defective address identifiers in said nonvolatile memory plus a predetermined increment value, inactivates a portion of said array whose address matches said defective address identifier plus said predetermined increment value, and also activates one of said redundant portions, and c) in a second mode, when the externally received address bits match one of said defective address identifiers in said non-volatile memory, activating two topologically adjacent ones of said redundant portions.
Claim 8
Dependent Claim
21 words
An integrated circuit memory as in claim 3, wherein said array of memory cells comprises at least 16 megabits of memory.
Claim 9
Dependent Claim
19 words
A method of operating an integrated circuit memory as in claim 3, wherein said predetermined increment value is 2.
Claim 10
Dependent Claim
22 words
An integrated circuit memory as in claim 3, wherein said predetermined increment value corresponds to the address difference between topologically adjacent elements.
Claim 11
Dependent Claim
179 words
A circuit for the selection of several redundant elements of an electrically erasable memory of the FLASH EEPROM type organized in rows and columns of memory cells, an "element" designating a row or a column, said redundant elements being designed to replace elements comprising defective cells, said elements to be replaced being identified respectively by particular values of a current address used to address said elements, one of said particular values being contained in non-volatile programmable memorizing means, wherein said selection circuit comprises: computation means for the computation, as a function of an input value equal to said value contained in said memorizing means, of the address value of at least one other element to be replaced, and comparison means to compare said current address with said memorized value and computed address value or values and to give comparison signals resulting from said comparisons, wherein said comparison signals condition the preparation of signals for the selection of associated redundant elements; and wherein said computation means are controllable so as to selectively provide a value identical to its input value.
Claim 12
Dependent Claim
179 words
A circuit for the selection of several redundant elements of an electrically erasable memory of the FLASH EEPROM type organized in rows and columns of memory cells, an "element" designating a row or a column, said redundant elements being designed to replace elements comprising defective cells, said elements to be replaced being identified respectively by particular values of a current address used to address said elements, one of said particular values being contained in non-volatile programmable memorizing means, wherein said selection circuit comprises: computation means for the computation, as a function of an input value equal to said value contained in said memorizing means, of the address value of at least one other element to be replaced, and comparison means to compare said current address with said memorized value and computed address value or values and to give comparison signals resulting from said comparisons, wherein said comparison signals condition the preparation of signals for the selection of associated redundant elements; and wherein said computation means are controllable so as to selectively provide a value identical to its input value.
Claim 13
Dependent Claim
33 words
A selection circuit according to claim 9, wherein said computation means comprise at least one incrementation circuit giving an output value equal to the sum of an input value and an incrementation value.
Claim 14
Dependent Claim
21 words
A selection circuit according to claim 9, comprising an incrementation circuit associated with each of said other elements to be replaced.
Claim 15
Dependent Claim
33 words
A selection circuit according to claim 9, wherein said incrementation circuit is formed by a combination of logic circuit designed to compute the sum of an input value and a fixed incrementation value.
Claim 16
Dependent Claim
31 words
A selection circuit according to claim 9, wherein said selection signals select topologically neighboring redundant rows and wherein said selection circuit comprises a circuit for the inhibition of said selection signals.
Claim 17
Dependent Claim
105 words
An electrically erasable programmable memory of the FLASH EEPROM type, comprising at least one selection circuit according to claim 9, wherein each stored value is associated with an invalidation indicator contained in a programmable, non-volatile memory cell, wherein when said invalidation indicator is in a first logic state, said selection signals are identical respectively to said comparison signals, wherein when said invalidation indicator is in a second logic state, said selection signals are inhibited except when an operation for the pre-erasure programming of the memory is carried out, in which case said computation means are controlled to give a value identical to said input value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |