US5281868A
Expired / Lapsed
US
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Memory redundancy addressing circuit for adjacent columns in a memory
Assignee: Micron Technology Inc
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Filing: 1992-08-18
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Granted: 1994-01-25
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Expires: 2012-08-18
Abstract
Abstract A circuit for automatically addressing and activating redundant circuits on an integrated circuit chip during testing, thereby improving efficient use of the space available for fuses and fuse pads. The circuit uses an integral number of fuses, whose blown and unblown combination represents 2**n possible states. Each state represents the address of a particular circuit or set of circuits gone bad on the chip which needs to be replaced. By employing an incrementor, the logical address representing the circuit or set of circuits physically adjacent to the bad circuit is also replaced. More sophisticated incrementors may be used to address more than one adjacent circuit or sets of circuits having a non-incremental address.
Inventors
- 👤 Donald Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:07
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/804; G11C29/808
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
63 words
A circuit for activating redundant circuits on an integrated circuit chip comprising: a plurality of fuses; means for logically interpreting the status of said fuse to correspond to an address, said address representing a faulty circuit located on said chip; means for calculating a second address corresponding to an adjacent circuit; means for enabling circuitry replacing said faulty circuit and said adjacent circuit.
Claim 2
Dependent Claim
63 words
A circuit for activating redundant circuits on an integrated circuit chip comprising: a plurality of fuses; means for logically interpreting the status of said fuse to correspond to an address, said address representing a faulty circuit located on said chip; means for calculating a second address corresponding to an adjacent circuit; means for enabling circuitry replacing said faulty circuit and said adjacent circuit.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein said integrated circuit chip comprises dynamic random access memory.
Claim 4
Dependent Claim
75 words
A circuit for activating redundant memory elements on an integerated circuit chip comprising: a plurality of fuses; means for logically interpreting the status of said fuses to correspond to an original address, said original address representing a first memory element; means for calculating at least one modified address corresponding to at least one physically adjacent memory element; means for replacing said first memory element and said adjacent memory element or elements with redundant memory elements.
Claim 5
Dependent Claim
75 words
A circuit for activating redundant memory elements on an integerated circuit chip comprising: a plurality of fuses; means for logically interpreting the status of said fuses to correspond to an original address, said original address representing a first memory element; means for calculating at least one modified address corresponding to at least one physically adjacent memory element; means for replacing said first memory element and said adjacent memory element or elements with redundant memory elements.
Claim 6
Dependent Claim
35 words
The circuit of claim 2 wherein said means for calculating comprises: means for applying a first modifier to said original address thereby generating a first modified address corresponding to a first physically adjacent memory element.
Claim 7
Dependent Claim
21 words
The circuit of claim 4 wherein said first modifier comprises: an addend, wherein said addend is any positive or negative integer.
Claim 8
Dependent Claim
13 words
The circuit of claim 4 wherein said means for applying comprises: an incrementor.
Claim 9
Dependent Claim
51 words
The circuit of claim 4 which further comprises: means for applying a second modifier to said original address thereby generating a second modified address corresponding to a second physically adjacent memory element, said second physically adjacent memory element located physically adjacent to said first memory element within said integerated circuit chip.
Claim 10
Dependent Claim
21 words
The circuit of claim 7 wherein said second modifier comprises: an addend, wherein said addend is any positive or negative integer.
Claim 11
Dependent Claim
17 words
The circuit of claim 7 wherein both of said means for applying comprises: at least one incrementor.
Claim 12
Dependent Claim
15 words
The circuit of claim 3 wherein each of said memory elements comprises: a memory cell.
Claim 13
Dependent Claim
20 words
The circuit of claim 3 wherein each of said memory elements comprises: a row comprising a plurality of memory cells.
Claim 14
Dependent Claim
20 words
The circuit of claim 3 wherein each of said memory elements comprises: a column comprising a plurality of memory cells.
Claim 15
Dependent Claim
103 words
A circuit for activating redundant memory elements on an integrated circuit chip comprising: a plurality of fuses; means for logically interpreting the status of said fuses to correspond to an original set of upper significant bits, said original set of upper significant bits corresponding to a first set of addresses representing a first set of memory elements; means for calculating at least one modified set of upper significant bits corresponding to a second set of addresses representing a second set of memory elements; means for replacing said first set of memory elements and said second set of memory elements with redundant memory elements.
Claim 16
Dependent Claim
103 words
A circuit for activating redundant memory elements on an integrated circuit chip comprising: a plurality of fuses; means for logically interpreting the status of said fuses to correspond to an original set of upper significant bits, said original set of upper significant bits corresponding to a first set of addresses representing a first set of memory elements; means for calculating at least one modified set of upper significant bits corresponding to a second set of addresses representing a second set of memory elements; means for replacing said first set of memory elements and said second set of memory elements with redundant memory elements.
Claim 17
Dependent Claim
15 words
The circuit of claim 13 wherein each of said memory elements comprises: a memory cell.
Claim 18
Dependent Claim
20 words
The circuit of claim 13 wherein each of said memory elements comprises: a row comprising a plurality of memory cells.
Claim 19
Dependent Claim
20 words
The circuit of claim 13 wherein each of said memory elements comprises: a column comprising a plurality of memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |