Fault detection and isolation system

Claim 2

An integrated circuit chip comprising in combination, (a) a first data processing chain having an input circuit and a first plurality of output circuits spaced at different points along said first data processing chain, at least one of said first plurality of output circuits being an intermediate output circuit, (b) a second data processing chain having an input circuit and a second plurality of output circuits spaced at different points along said second data processing chain, at least one of said second plurality of output circuits being an intermediate output circuit, (c) input signal connections for coupling external signals to said chip, (d) means connecting at least some of said input signal connections to said input circuits of both of said first and second data processing chains, (e) at least one comparator circuit having a first input circuit permanently coupled to said at least one intermediate output circuit of said first processing chain for receiving signals therefrom, a second input circuit permanently coupled to said at least one intermediate output circuit of said second processing chain for receiving signals therefrom, and an output circuit, said at least one intermediate output circuit points of said data processing chains being the equivalent to each other along the processing path in each chain, and said comparator producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said comparator represent different data and producing at its output circuit a second signal when the input signals to the said comparator represent the same data.

Claim 3

An integrated circuit chip as defined in claim 1 further including at least another comparator circuit having, a first input circuit permanently coupled to another of said first plurality of output circuits of said first processing chain for receiving signals therefrom, a second input circuit permanently coupled to another of said second plurality of output circuits of said second processing chain for receiving signals therefrom, and an output circuit, said at least another comparator circuit producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said comparator represent different data and producing at its output circuit a second signal when the input signals to the said comparator represent the same data, both of said at least one comparator circuit and said at least another comparator circuit functioning simultaneously.

Claim 4

An integrated circuit chip as defined in claim 1 wherein one of said first plurality of output circuits is the final output circuit of said first data processing chain, and wherein one of said second plurality of output circuits is the final output circuit of said second data processing chain.

Claim 5

An integrated circuit chip comprising in combination, (a) a first data processing chain having an input circuit and a first plurality of output circuits spaced at different points along said first data processing chain, at least one of said first plurality of output circuits being an intermediate output circuit, (b) a second data processing chain having an input circuit and a second plurality of output circuits spaced at different points along said second data processing chain, at least one of said second plurality of output circuits being an intermediate output circuit, (c) input signal connections for coupling external signals to said chip, (d) means connecting at least some of said input signal connections to said input circuits of both of said first and second data processing chains, (e) at least one comparator circuit having a first input circuit coupled to said at least one intermediate output circuit of said first processing chain for receiving signals therefrom, a second input circuit coupled to said at least one intermediate output circuit of said second processing chain for receiving signals therefrom, and an output circuit, said at least one intermediate output circuit points of said data processing chains being the equivalent to each other along the processing path in each chain, and said comparator producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said comparator represent different data and producing at its output circuit a second signal when the input signals to the said comparator represent the same data, (f) at least another comparator circuit having, a first input circuit coupled to another of said first plurality of output circuits of said first processing chain for receiving signals therefrom, a second input circuit coupled to another of said second plurality of output circuits of said second chain for receiving signals therefrom, and an output circuit, said at least another comparator circuit producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said another comparator represent different data and producing at its output circuit a second signal when the input signals to the said another comparator represent the same data, (g) an error encoding circuit having a plurality of input circuits and an output circuit, the output circuits of said at least one comparator circuit and said at least another comparator circuit being coupled to separate ones of said plurality of input circuits of said error encoding circuit, and said error encoding circuit being effective responsive to receipt of said first and second signals from said comparator circuits to generate at its output circuit encoded signals designating the sources of processing errors in said integrated circuit chip.

Claim 6

An integrated circuit chip comprising in combination, (a) a first data processing chain having an input circuit and a first plurality of output circuits spaced at different points along said first data processing chain, at least one of said first plurality of output circuits being an intermediate output circuit, (b) a second data processing chain having an input circuit and a second plurality of output circuits spaced at different points along said second data processing chain, at least one of said second plurality of output circuits being an intermediate output circuit, (c) input signal connections for coupling external signals to said chip, (d) means connecting at least some of said input signal connections to said input circuits of both of said first and second data processing chains, (e) at least one comparator circuit having a first input circuit coupled to said at least one intermediate output circuit of said first processing chain for receiving signals therefrom, a second input circuit coupled to said at least one intermediate output circuit of said second processing chain for receiving signals therefrom, and an output circuit, said at least one intermediate output circuit points of said data processing chains being the equivalent to each other along the processing path in each chain, and said comparator producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said comparator represent different data and producing at its output circuit a second signal when the input signals to the said comparator represent the same data, (f) at least another comparator circuit having, a first input circuit coupled to another of said first plurality of output circuits of said first processing chain for receiving signals therefrom, a second input circuit coupled to another of said second plurality of output circuits of said second chain for receiving signals therefrom, and an output circuit, said at least another comparator circuit producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said another comparator represent different data and producing at its output circuit a second signal when the input signals to the said another comparator represent the same data, (g) an error encoding circuit having a plurality of input circuits and an output circuit, the output circuits of said at least one comparator circuit and said at least another comparator circuit being coupled to separate ones of said plurality of input circuits of said error encoding circuit, and said error encoding circuit being effective responsive to receipt of said first and second signals from said comparator circuits to generate at its output circuit encoded signals designating the sources of processing errors in said integrated circuit chip.

Claim 7

An integrated circuit chip as defined in claims 1, 2, 3 or 4 wherein said chip is a VLSI.

Claim 8

An integrated circuit chip as defined in claim 3 wherein said chip further includes at least one fault detector circuit having input circuits and an output circuit, said input circuits being coupled to selected ones of said input signal connections for coupling external signals to said chip, and said output circuit being coupled to one of said plurality of input circuits of said error encoding circuit, said at least one fault detector being operative to monitor and check for occurrence of errors in input signals to said chip which have not been processed through said data processing chains.

Claim 9

A plurality of integrated circuit chips as defined in claim 4 in which each said chip is an independent part of a total complex, said total complex also comprising, (a) an error handling integrated circuit chip as defined in claim 6, (b) interconnection means connecting the error encoding circuit output circuit of each of said plurality of integrated circuit chips as defined in claim 3 to the input circuit of said error handling chip, (c) interconnection means conducting power, data signals and timing signals to said plurality of integrated circuit chips, whereby, said error handling chip processes said encoded error signals and is effective responsive to the received encoded error signals to generate at its final output circuit final encoded signals designating the sources of errors with respect to specific ones of said plurality of integrated circuit chips, and with respect to specific ones of said interconnection means, and with respect to said sources of power, timing signals and data signals.

Claim 10

A plurality of integrated circuit chips as defined in claim 6 in which each said chip is an independent part of a total complex, said total complex also comprising, (a) an error handling integrated circuit chip as defined in claim 6, (b) interconnection means connecting the error encoding circuit output circuit of each of said plurality of integrated circuit chips as defined in claim 6 to the input circuit of said error handling chip, (c) interconnection means conducting power, data signals and timing signals to said plurality of integrated circuit chips, whereby, said error handling chip processes said encoded error signals and is effective responsive to the received encoded error signals to generate at its final output circuit final encoded signals designating the sources of errors with respect to specific ones of said plurality of integrated circuit chips, and with respect to specific ones of said interconnection means, and with respect to said sources of power, timing signals and data signals.

Claim 11

A plurality of integrated circuit chips as defined in claim 4 in which each said chip is an independent part of a total complex, said total complex also comprising, (a) an error handling integrated circuit chip as defined in claim 3, (b) interconnection means connecting the error encoding circuit output circuit of each of said plurality of integrated circuit chips as defined in claim 3 to the input circuit of said error handling chip, (c) interconnection means conducting power, data signals and timing signals to said plurality of integrated circuit chips, whereby, said error handling chip processes said encoded error signals and is effective responsive to the received encoded error signals to generate at an output circuit final encoded signals designating the sources of errors with respect to specific ones of said plurality of integrated circuit chips, and with respect to specific ones of said interconnection means, and with respect to said sources of power, timing signals and data signals.

Claim 12

A plurality of integrated circuit chips as defined in claim 6 in which each said chip is an independent part of a total complex, said total complex also comprising, (a) an error handling integrated circuit chip as defined in claim 4, (b) interconnection means connecting the error encoding circuit output circuit of each of said plurality of integrated circuit chips as defined in claim 6 to the input circuit of said error handling chip, (c) interconnecting means conducting power, data signals and timing signals to said plurality of integrated circuit chips, whereby, said error handling chip processes said encoded error signals and is effective responsive to the received encoded error signals to generate at an output circuit final encoded signals designating the sources of errors with respect to specific ones of said plurality of integrated circuit chips, and with respect to specific ones of said interconnection means, and with respect to said sources of power, timing signals and data signals.

Claim 13

Integrated circuit chips as defined in any of claims 1, 4, 6, 7, 8, 9 or 10 wherein the functional logic of said second data processing chain is a duplicate of the functional logic of said first data processing chain.

Claim 14

Integrated circuit chips as defined in any of claims 1, 4, 6, 7, 8, 9 or 10 wherein the functional logic of said second data processing chain is the duplicate complementary logic to the functional logic of said first data processing chain.

Claim 15

An integrated circuit chip as defined in claim 1, 2, 3, or 4 wherein said chip is a VLSI, and wherein the functional logic of said second data processing chain is a duplicate of the functional logic of said first data processing chain.

Claim 16

An integrated circuit chip as defined in claim 1, 2, 3, or 4 wherein said chip is VLSI, and wherein the functional logic of said second data processing chain is the duplicate complementary logic to the functional logic of said first data processing chain.