Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same

Claim 2

A semiconductor package comprising: (a) an insulating substrate having a device hole penetrating, with a monotonic side wall substantially vertical to a surface of the insulating substrate, through a central portion thereof; (b) wiring layers disposed on a surface of said insulating substrate; (c) a semiconductor chip thinner than said insulating substrate, having bonding pads, said semiconductor chip being disposed in said device hole such that a bottom thereof is exposed at said device hole so that the bottom level is flush with a bottom plane of said insulating substrate, and such that a top surface of the semiconductor chip does not directly contact the insulating substrate; (d) inner-joint-conductors for connecting at least part of said bonding pads to corresponding said wiring layers; and (e) connection lands connected to said wiring layers.

Claim 3

A semiconductor package comprising: an insulating substrate having a device hole penetrating through a central portion thereof; wiring layers disposed on a surface of said insulating substrate; a semiconductor chip thinner than said insulating substrate, having bonding pads, said semiconductor chip being disposed in said device hole such that a bottom thereof is exposed at said device hole so that the bottom level is flush with a bottom plane of said insulating substrate; inner-joint-conductors for connecting at least part of said bonding pads to corresponding said wiring layers; connection lands connected to said wiring layers; and a sealing resin filled in a gap between a sidewall of the device hole and said semiconductor chip configured such that a bottom thereof is flush with the bottom plane of said insulating substrate.

Claim 4

A semiconductor package comprising: an insulating substrate having a device hole penetrating through a central portion thereof; wiring layers disposed on a surface of said insulating substrate; a semiconductor chip thinner than said insulating substrate, having bonding pads, said semiconductor chip being disposed in said device hole such that a bottom thereof is exposed at said device hole so that the bottom level is flush with a bottom plane of said insulating substrate; inner-joint-conductors for connecting at least part of said bonding pads to corresponding said wiring layers; connection lands connected to said wiring layers; and a sealing resin filled in a gap between a sidewall of the device hole and said semiconductor chip configured such that a bottom thereof is flush with the bottom plane of said insulating substrate.

Claim 5

The package of claim 1 , further comprising through holes formed just below said connection lands, within said insulating substrate.

Claim 6

A multi-chip module comprising: (a) a first insulating substrate having a first device hole penetrating, with a monotonic side wall substantially vertical to a surface of the first insulating substrate, through a central portion thereof; (b) first wiring layers disposed on a surface of said first insulating substrate; (c) a first semiconductor chip thinner than said first insulating substrate, having first bonding pads, said first semiconductor chip being disposed in said device hole configured such that a bottom thereof is flush with a bottom plane of said first insulating substrate, and such that a top surface of the first semiconductor chip does not directly contact the first insulating substrate; (d) first inner-joint-conductors for connecting at least part of said first bonding pads to corresponding said first wiring layers; (e) first connection lands connected to said first wiring layers (f) a second insulating substrate having a second device hole penetrating, with a monotonic side wall substantially vertical to a surface of the second insulating substrate, through a central portion thereof, disposed above said first insulating substrate; (g) second wiring layers disposed on a surface of said second insulating substrate; (h) a second semiconductor chip thinner than said second insulating substrate, having second bonding pads, said second semiconductor chip being disposed in said second device hole configured such that a bottom thereof is flush with a bottom plane of said second insulating substrate, and such that a top surface of the second semiconductor chip does not directly contact the second insulating substrate; (i) second inner-joint-conductors for connecting at least part of said second bonding pads to corresponding said second wiring layers; and (j) second connection lands connected to said second wiring layers, electrically connected to said first connection lands.

Claim 7

A multi-chip module comprising: (a) a first insulating substrate having a first device hole penetrating, with a monotonic side wall substantially vertical to a surface of the first insulating substrate, through a central portion thereof; (b) first wiring layers disposed on a surface of said first insulating substrate; (c) a first semiconductor chip thinner than said first insulating substrate, having first bonding pads, said first semiconductor chip being disposed in said device hole configured such that a bottom thereof is flush with a bottom plane of said first insulating substrate, and such that a top surface of the first semiconductor chip does not directly contact the first insulating substrate; (d) first inner-joint-conductors for connecting at least part of said first bonding pads to corresponding said first wiring layers; (e) first connection lands connected to said first wiring layers (f) a second insulating substrate having a second device hole penetrating, with a monotonic side wall substantially vertical to a surface of the second insulating substrate, through a central portion thereof, disposed above said first insulating substrate; (g) second wiring layers disposed on a surface of said second insulating substrate; (h) a second semiconductor chip thinner than said second insulating substrate, having second bonding pads, said second semiconductor chip being disposed in said second device hole configured such that a bottom thereof is flush with a bottom plane of said second insulating substrate, and such that a top surface of the second semiconductor chip does not directly contact the second insulating substrate; (i) second inner-joint-conductors for connecting at least part of said second bonding pads to corresponding said second wiring layers; and (j) second connection lands connected to said second wiring layers, electrically connected to said first connection lands.

Claim 8

The multi-chip module of claim 4 , further comprising a first sealing resin filled in a gap between a sidewall of said first device hole and said first semiconductor chip configured such that a bottom thereof is flush with the bottom plane of said first insulating substrate.

Claim 9

The multi-chip module of claim 5 , further comprising second sealing resin filled in a gap between a sidewall of said second device hole and said second semiconductor chip configured such that a bottom thereof is flush with the bottom plane of said second insulating substrate.

Claim 10

The multi-chip module of claim 4 , further comprising: a first through hole formed just below said first connection lands, in said first insulating substrate; and a second through hole formed just above said second connection lands, in said second insulating substrate.

Claim 11

The multi-chip module of claim 7 , further comprising: first stud conductors buried in each of said first through holes; and a MCM substrate having package wirings electrically connected to said first stud conductors.

Claim 12

The multi-chip module of claim 8 , further comprising: second stud conductors buried in said second through holes; a third insulating substrate having a third device hole, penetrating through a central portion thereof, disposed above said second insulating substrate; third wiring layers disposed on a surface of said third insulating substrates; a third semiconductor chip thinner than said third insulating substrate, having third bonding pads, said third semiconductor chip being disposed in said third device hole such that a bottom thereof is flush with a bottom plane of said third insulating substrate; third inner-joint-conductors for connecting at least part of said third bonding pads to corresponding said third wiring layers; third connection lands connected to said third wiring layers, electrically connected to said second connection lands; third through holes formed just below said third connection lands, in said third insulating substrate; and third stud conductors buried in said third through holes, electrically connected to said second stud conductors.

Claim 13

The multi-chip module of claim 4 , wherein thicknesses of said first and second insulating substrates are 30 μm-120 μm, respectively.

Claim 14

The multi-chip module of claim 4 , wherein thicknesses of said first and second semiconductor chips are 10 μm-110 μm, respectively.

Claim 15

The multi-chip module of claim 4 wherein said first and second wiring layers are disposed in a mirror-symmetrically topology on the surface of said first and second insulating substrates, respectively.

Claim 16

The multi-chip module of claim 9 , wherein said second and third wiring layers are disposed in a mirror-symmetrically topology on the surface of said second and third insulating substrates, respectively.

Claim 17

The multi-chip module of claim 9 , wherein said second and third semiconductor chips are in contact with each other through bottom faces thereof.

Claim 18

The multi-chip module of claim 4 , wherein said second insulating substrate is shifted by a predetermined distance along a plane parallel to said first insulating substrate relative thereto.

Claim 19

The multi-chip module of claim 9 , wherein said third insulating substrate is shifted by a predetermined distance along a plane parallel to said second insulating substrate relative thereto.

Claim 20

A multi-chip module comprising: (a) a first insulating substrate; (b) first wiring layers disposed on a surface of said first insulating substrate; (c) a first semiconductor chip having first bonding pads, disposed above a main surface of said first insulating substrate; (d) first inner-joint-conductors for electrically connecting at least part of said first bonding pads to corresponding said first wiring layers; (e) a first sealing member filled between said first insulating substrate and said first semiconductor chip; (f) a second insulating substrate shifted by a predetermined distance along a plane parallel to said first insulating substrate relative thereto, having second wiring layers electrically connected to said first wiring layers on a main surface thereof; (g) a second semiconductor chip having second bonding pads, disposed above said main surface of said second insulating substrate; (h) second inner-joint-conductors for electrically connecting at least part of said second bonding pads to corresponding said second wiring layers; and (i) a second sealing member filled between said second insulating substrate and said second semiconductor chip.

Claim 21

A multi-chip module comprising: (a) a first insulating substrate; (b) first wiring layers disposed on a surface of said first insulating substrate; (c) a first semiconductor chip having first bonding pads, disposed above a main surface of said first insulating substrate; (d) first inner-joint-conductors for electrically connecting at least part of said first bonding pads to corresponding said first wiring layers; (e) a first sealing member filled between said first insulating substrate and said first semiconductor chip; (f) a second insulating substrate shifted by a predetermined distance along a plane parallel to said first insulating substrate relative thereto, having second wiring layers electrically connected to said first wiring layers on a main surface thereof; (g) a second semiconductor chip having second bonding pads, disposed above said main surface of said second insulating substrate; (h) second inner-joint-conductors for electrically connecting at least part of said second bonding pads to corresponding said second wiring layers; and (i) a second sealing member filled between said second insulating substrate and said second semiconductor chip.

Claim 22

The multi-chip module of claim 17 , wherein thicknesses of said first and second semiconductor chips are 10 μm-150 μm, respectively.

Claim 23

The multi-chip module of claim 17 , wherein thicknesses of said first and second insulating substrates are 30 μm-100 μm, respectively.

Claim 24

The multi-chip module of claim 17 , wherein a thickness of said semiconductor chip is 30 μm-120 μm.

Claim 25

The package of claim 1 , wherein a thickness of said package is 120 μm-200 μm.