US5334875A
Expired / Lapsed
US
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Stacked semiconductor memory device and semiconductor memory module containing the same
Assignee: Hitachi Ltd
•
Filing: 1993-03-02
•
Granted: 1994-08-02
•
Expires: 2013-03-02
Abstract
Abstract There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
Inventors
- 👤 Toshio Sugano
- 👤 Kohji Nagaoka
- 👤 Seiichiro Tsukui
- 👤 Yoshiaki Wakashima
- 👤 Michio Tanimoto
- 👤 Masayuki Watanabe
- 👤 Suguru Sakaguchi
- 👤 Kunihiko Nishi
- 👤 Aizo Kaneda
- 👤 Kohji Serizawa
- 👤 Michiharu Honda
- 👤 Tohru Yoshida
- 👤 Takeshi Komaru
- 👤 Atsushi Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:53
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/06; H; H10; H10B; H10B80/00; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/657; H10W90/00; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/144; H05K1/18; H05K1/182; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3421; H05K3/36; H05K3/361; H05K3/363; H10W72/00; H10W72/01; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/60; H10W90/20; H10W90/22; H10W90/284; H10W90/297; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 59
Claim 1
Independent Claim
236 words
A semiconductor memory device comprising: first and second semiconductor memory chips which are stacked one above the other, each of said memory chips having first and second principal surfaces with a plurality of first electrodes and a second electrode being located on the first principal surface; and first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors, wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, wherein said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, wherein said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, wherein said first electrodes of said first memory chip are electrically connected to respective electrodes of said first electrodes of said second memory chip via said first and second conductors, and wherein said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip.
Claim 2
Dependent Claim
236 words
A semiconductor memory device comprising: first and second semiconductor memory chips which are stacked one above the other, each of said memory chips having first and second principal surfaces with a plurality of first electrodes and a second electrode being located on the first principal surface; and first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors, wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, wherein said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, wherein said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, wherein said first electrodes of said first memory chip are electrically connected to respective electrodes of said first electrodes of said second memory chip via said first and second conductors, and wherein said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip.
Claim 3
Dependent Claim
53 words
A semiconductor memory device according to claim 1, wherein a distance between said first surface and said second surface of each of said first and second connectors is larger than that between said first principal surface and said second principal surface of the associated one of said first and second semiconductor memory chips.
Claim 4
Dependent Claim
28 words
A semiconductor memory device according to claim 1, wherein said second electrode of said first semiconductor memory chip receives a signal for selecting said first semiconductor memory chip.
Claim 5
Dependent Claim
24 words
A semiconductor memory device according to claim 3, wherein said signal for selecting said first semiconductor memory chip is a row address strobe signal.
Claim 6
Dependent Claim
23 words
A semiconductor memory device according to claim 2, wherein said signal for selecting said first semiconductor memory chip is a data input/output signal.
Claim 7
Dependent Claim
28 words
A semiconductor memory device according to claim 1, wherein said second electrode of said second semiconductor memory chip receives a signal for selecting said second semiconductor memory chip.
Claim 8
Dependent Claim
24 words
A semiconductor memory device according to claim 6, wherein said signal for selecting said second semiconductor memory chip is a row address strobe signal.
Claim 9
Dependent Claim
23 words
A semiconductor memory device according to claim 7, wherein said signal for selecting said second semiconductor memory chip is a data input/output signal.
Claim 10
Dependent Claim
46 words
A semiconductor memory device according to claim 1, wherein said first electrodes and said second electrode are electrically connected to said first conductors by means of leads which each have one end electrically connected to an electrode and another end electrically connected to a first conductor.
Claim 11
Dependent Claim
50 words
A semiconductor memory device according to claim 9, wherein each of said first conductors is electrically connected to a respective one of said second conductors by means of a part of the lead electrically connected to said first conductor which is extended continuously from said another end of said lead.
Claim 12
Dependent Claim
35 words
A semiconductor memory device according to claim 9, wherein each of said first conductors is electrically connected to a respective one of said second conductors by means of a through-hole formed in the associated connector.
Claim 13
Dependent Claim
52 words
A semiconductor memory device according to claim 9, further comprising: another plurality of leads, each having one end which is not electrically connected to said electrodes of said first and second semiconductor memory chips and another end connected to a respective one of said first conductors of said first and second connectors.
Claim 14
Dependent Claim
28 words
A semiconductor memory device according to claim 1, further comprising: a resin for sealing said first principal surfaces of said first and second memory chips and said electrodes.
Claim 15
Dependent Claim
20 words
A semiconductor memory device according to claim 1, wherein each of said first and second electrodes is a bump electrode.
Claim 16
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein four of said connectors are stacked.
Claim 17
Dependent Claim
16 words
A semiconductor memory device according to claim 1, wherein said connectors are made of glass epoxy.
Claim 18
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein said connectors are made of ceramic.
Claim 19
Dependent Claim
17 words
A semiconductor memory device according to claim 1, wherein said connectors are made of a polyimide resin.
Claim 20
Dependent Claim
261 words
A semiconductor memory device comprising: first and second semiconductor memory chips which are stacked one above the other, each having first and second principal surfaces, each of said first and second semiconductor memory chips having a plurality of first electrodes and a second electrode on said first principal surface; first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors; and a substrate having a main surface and a rear surface, a plurality of first and second wiring patterns formed on said main surface, wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, wherein said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, wherein said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, wherein said first electrodes of said first memory chip are electrically connected to each of said first electrodes of said second memory chip via said first and second conductors, and wherein said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip.
Claim 21
Dependent Claim
261 words
A semiconductor memory device comprising: first and second semiconductor memory chips which are stacked one above the other, each having first and second principal surfaces, each of said first and second semiconductor memory chips having a plurality of first electrodes and a second electrode on said first principal surface; first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors; and a substrate having a main surface and a rear surface, a plurality of first and second wiring patterns formed on said main surface, wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, wherein said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, wherein said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, wherein said first electrodes of said first memory chip are electrically connected to each of said first electrodes of said second memory chip via said first and second conductors, and wherein said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip.
Claim 22
Dependent Claim
97 words
A semiconductor memory device according to claim 19, wherein said substrate has a plurality of first terminals and a plurality of second terminals, wherein each of said first electrodes of said first and second memory chips is electrically connected to a respective terminal of said first terminals via said wiring patterns, wherein said second electrode of said first memory chip is electrically connected to one of said second terminals via said wiring pattern, and wherein said second electrode of said second memory chip is electrically connected to another one of said second terminals via said wiring pattern.
Claim 23
Dependent Claim
53 words
A semiconductor memory device according to claim 19, wherein a distance between said first surface and said second surface of each of said first and second conductors is larger than that between said first principal surface and said second principal surface of the associated one of said first and second semiconductor memory chips.
Claim 24
Dependent Claim
28 words
A semiconductor memory device according to claim 19, wherein said second electrode of said first semiconductor memory chip receives a signal for selecting said first semiconductor memory chip.
Claim 25
Dependent Claim
24 words
A semiconductor memory device according to claim 22, wherein said signal for selecting said first semiconductor memory chip is a row address strobe signal.
Claim 26
Dependent Claim
23 words
A semiconductor memory device according to claim 22, wherein said signal for selecting said first semiconductor memory chip is a data input/output signal.
Claim 27
Dependent Claim
28 words
A semiconductor memory device according to claim 19, wherein said second electrode of said second semiconductor memory chip receives a signal for selecting said second semiconductor memory chip.
Claim 28
Dependent Claim
24 words
A semiconductor memory device according to claim 25, wherein said signal for selecting said second semiconductor memory chip is a row address strobe signal.
Claim 29
Dependent Claim
23 words
A semiconductor memory device according to claim 26, wherein said signal for selecting said second semiconductor memory chip is a data input/output signal.
Claim 30
Dependent Claim
46 words
A semiconductor memory device according to claim 19, wherein said first electrodes and said second electrodes are electrically connected to said first conductors by means of leads which each have one end electrically connected to an electrode and another end electrically connected to a first conductor.
Claim 31
Dependent Claim
50 words
A semiconductor memory device according to claim 28, wherein each of said first conductors is electrically connected to a respective one of said second conductors by means of a part of the lead electrically connected to said first conductor which is extended continuously from said another end of said lead.
Claim 32
Dependent Claim
34 words
A semiconductor memory device according to claim 28, wherein each of said first conductors is electrically connected to a respective one of said second conductors by means of a through-hole formed in said connectors.
Claim 33
Dependent Claim
52 words
A semiconductor memory device according to claim 28, further comprising: another plurality of leads, each having one end which is not electrically connected to said electrodes of said first and second semiconductor memory chips and another end connected to a respective one of said first conductors of said first and second connectors.
Claim 34
Dependent Claim
28 words
A semiconductor memory device according to claim 19, further comprising: a resin for sealing said first principal surfaces of said first and second memory chips and said electrodes.
Claim 35
Dependent Claim
20 words
A semiconductor memory device according to claim 19, wherein each of said first and second electrodes is a bump electrode.
Claim 36
Dependent Claim
15 words
A semiconductor memory device according to claim 19, wherein four of said connectors are stacked.
Claim 37
Dependent Claim
16 words
A semiconductor memory device according to claim 19, wherein said connector is made of glass epoxy.
Claim 38
Dependent Claim
15 words
A semiconductor memory device according to claim 19, wherein said connectors are made of ceramic.
Claim 39
Dependent Claim
17 words
A semiconductor memory device according to claim 19, wherein said connectors are made of a polyimide resin.
Claim 40
Dependent Claim
272 words
A semiconductor memory module comprising: first and second semiconductor memory devices, each of said first and second semiconductor memory devices comprising: first and second semiconductor memory chips which are stacked one above the other, each of said memory chips having first and second principal surfaces with a plurality of first electrodes and a second electrode being located on the first principal surface; first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors, wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, and wherein said first electrodes of said first memory chip are electrically connected to respective electrodes of said first electrodes of said second memory chip via said first and second conductors, said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip; and a substrate having a main surface and a rear surface, said semiconductor memory devices being mounted on said main surface of said substrate.
Claim 41
Dependent Claim
272 words
A semiconductor memory module comprising: first and second semiconductor memory devices, each of said first and second semiconductor memory devices comprising: first and second semiconductor memory chips which are stacked one above the other, each of said memory chips having first and second principal surfaces with a plurality of first electrodes and a second electrode being located on the first principal surface; first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors, wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, and wherein said first electrodes of said first memory chip are electrically connected to respective electrodes of said first electrodes of said second memory chip via said first and second conductors, said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip; and a substrate having a main surface and a rear surface, said semiconductor memory devices being mounted on said main surface of said substrate.
Claim 42
Dependent Claim
122 words
A semiconductor memory module according to claim 38, further comprising: a logic decoder having a plurality of terminals, and wherein said substrate has a plurality of first terminals and a plurality of second terminals, wherein each of said first electrodes which are electrically connected to each other, on said first and second memory chips of said first memory device and each of said first electrodes, which are electrically connected to each other, on said fist and second memory chips of said second memory device are electrically connected to each of said first terminals, and wherein each of said second electrodes of said first and second memory chips is electrically connected to a respective one of said second terminals via said logic decoder.
Claim 43
Dependent Claim
53 words
A semiconductor memory module according to claim 38, wherein a distance between said first surface and said second surface of each of said first and second connectors is larger than that between said first principal surface and said second principal surface of the associated one of said first and second semiconductor memory chips.
Claim 44
Dependent Claim
42 words
A semiconductor memory module according to claim 38, wherein each of said second electrodes of said first and second semiconductor memory chips of said first semiconductor memory device receives a signal for selecting each of said first and second semiconductor memory chips.
Claim 45
Dependent Claim
41 words
A semiconductor memory module according to claim 38, wherein each of said second electrodes of said first and second semiconductor memory chips of second semiconductor memory device receives a signal for selecting each of said first and second semiconductor memory chips.
Claim 46
Dependent Claim
45 words
A semiconductor memory module according to claim 38, wherein said first electrodes and said second electrodes are electrically connected to said first conductors by means of leads which each have one end electrically connected to an electrode and another electrically connected to a first conductor.
Claim 47
Dependent Claim
50 words
A semiconductor memory module according to claim 43, wherein each of said first conductors is electrically connected to a respective one of said second conductors by means of a part of the lead electrically connected to said first conductor which is extended continuously from said another end of said lead.
Claim 48
Dependent Claim
35 words
A semiconductor memory module according to claim 43, wherein each of said first conductors is electrically connected to a respective one of said second conductors by means of a through-hole formed in the associated connector.
Claim 49
Dependent Claim
55 words
A semiconductor memory module according to claim 38, further comprising: another plurality of leads, each having one end which is not electrically connected to said first and second electrodes of said first and second semiconductor memory chips and another end connected to a respective one of said first conductors of said first and second connectors.
Claim 50
Dependent Claim
28 words
A semiconductor memory module according to claim 38, further comprising: a resin for sealing said first principal surfaces of said first and second memory chips and said electrodes.
Claim 51
Dependent Claim
20 words
A semiconductor memory module according to claim 38, wherein each of said first and second electrodes is a bump electrode.
Claim 52
Dependent Claim
21 words
A semiconductor memory module according to claim 38, wherein each of said semiconductor devices has four connectors stacked one above another.
Claim 53
Dependent Claim
16 words
A semiconductor memory module according to claim 38, wherein said connectors are made of glass epoxy.
Claim 54
Dependent Claim
15 words
A semiconductor memory module according to claim 38, wherein said connectors are made of ceramic.
Claim 55
Dependent Claim
17 words
A semiconductor memory module according to claim 38, wherein said connectors are made of a polyimide resin.
Claim 56
Dependent Claim
150 words
A semiconductor memory module according to claim 38, wherein said substrate has a plurality of first terminals and a plurality of second terminals, wherein said first electrodes which are electrically connected to each other, on said first and second memory chips of said first memory device are electrically connected to one of said first terminals, wherein said first electrodes, which are electrically connected to each other, on said first and second memory chips of said second memory device are electrically connected to another one of said first terminals, wherein said second electrodes formed on said first memory chips of said first and second memory devices are electrically connected to each other and to one of said second terminals, and wherein said second electrodes formed on said second memory chips of said first and second memory devices are electrically connected to each other and to another one of said second terminals.
Claim 57
Dependent Claim
62 words
A semiconductor memory module according to claim 53, wherein each of said first electrodes, which are electrically connected to each other, on said first and second memory chips of said first memory device and each of said first electrodes, which are electrically connected to each other, on said first and second memory chips of said second semiconductor device receives data input/output signals.
Claim 58
Dependent Claim
30 words
A semiconductor memory module according to claim 53, wherein said second electrode of said first memory chips are electrically connected to each other and receive a row address strobe signal.
Claim 59
Dependent Claim
30 words
A semiconductor memory module according to claim 53, wherein said second electrodes of said second memory chips are electrically connected to each other and receive a column address strobe signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-01 | 1998-01-31 | 1998-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-01 | 2002-01-31 | 2002-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-01 | 2006-01-31 | 2006-08-02 | $7700.00 | Window Closed / Lapsed |