Method of constructing stacked packages

Claim 2

A semiconductor assembly, comprising: a base substrate having a first surface including a plurality of bond pads; a first stacked substrate having a first surface and a second surface, at least one of said first surface and second surface of said first stacked substrate including a plurality of bond pads; a first semiconductor die disposed on said first surface of said first stacked substrate, said first semiconductor die having an active surface, a second surface, and a plurality of bond pads located on the active surface; a second semiconductor die having a first surface facing said first surface of said base substrate, said first surface having a plurality of bond pads located thereon, said second semiconductor die disposed on said second surface of said first stacked substrate; at least one first intercoupler connecting said at least one of said plurality bond pads of said first surface of said first stacked substrate and said plurality of bond pads on said second surface of said first stacked substrate, and at least one of said plurality of bond pads of said first semiconductor die; at least one second intercoupler connecting said base substrate and said first stacked substrate, said at least one second intercoupler positioning said first stacked substrate substantially parallel to said base substrate; a second stacked substrate having a first surface including a plurality of bond pads and having a second surface including a plurality of bond pads; at third semiconductor die disposed on said first surface of said second stacked substrate, said third semiconductor die having a plurality of bond pads located thereon; a fourth semiconductor die disposed on said second surface of said second stacked substrate, said fourth semiconductor die having a plurality of bond pads located thereon; at least one fourth intercoupler connecting said at least one of said plurality of bond pads on the first surface of said second stacked substrate and said plurality of bond pads of said second surface of said second stacked substrate, and at least one of said plurality of bond pads of said fourth semiconductor die; and at least one fifth intercoupler connecting said second stacked substrate and one of said first surface of said first stacked substrate, said second surface of said first stacked substrate, and said first surface of said base substrate, said at least one fifth intercoupler separating one of said second stacked substrate from said first surface of said first stacked substrate, said second surface of said first stacked substrate, or said first surface of said base substrate.

Claim 3

The semiconductor assembly of claim 1 , wherein said at least one second intercoupler is disposed intermediate at least one of said plurality of bond pads of said first stacked substrate and said plurality bond pads of said second surface of first stacked substrate, and at least one of said plurality of bond pads of said base substrate.

Claim 4

The semiconductor assembly of claim 1 , wherein said at least one first intercoupler connects at least one bond pad of the plurality of bond pads of said second semiconductor die and at least one bond pad of the plurality of bond pads of said first semiconductor die.

Claim 5

The semiconductor assembly of claim 1 , wherein said first semiconductor die is located on and electrically connected to said first surface of said first stacked substrate.

Claim 6

The semiconductor assembly of claim 1 , wherein said second surface of said first stacked substrate includes a plurality of bond pads; and wherein said first semiconductor die is located on and connected to said second surface of said first stacked substrate.

Claim 7

The semiconductor assembly of claim 1 , wherein said at least one first intercoupler includes one of solder, conductive adhesives, Z-axis conductive material, flex-contacts, spring contacts, wire bonds, and TAB tape.

Claim 8

The semiconductor assembly of claim 1 , wherein said base substrate further comprises a second surface having a plurality of bond pads located thereon.

Claim 9

The semiconductor assembly of claim 7 , further comprising connections attached to said plurality of bond pads of said second surface of said base substrate for connection with external electrical circuitry.

Claim 10

The semiconductor assembly of claim 8 , further comprising a plurality of trace leads located on said base substrate connecting said plurality of bond pads of said first surface of said base substrate and said plurality of bond pads of said second surface of said base substrate.

Claim 11

The semiconductor assembly of claim 1 , further comprising: a base semiconductor die having a plurality of bond pads and disposed on said base substrate first surface; and at least one third intercoupler connecting said at least one of said plurality of bond pads of said first surface of said base substrate and at least one of said plurality of bond pads of said first semiconductor die.

Claim 12

A semiconductor assembly comprising: a base substrate having a first surface including a plurality of bonds pads thereon, a second surface including a plurality of bond pads thereon, and a plurality of traces, at least one trace of said plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of said plurality of bond pads on said second surface of said base substrate; a first stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said first stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a first semiconductor die disposed on said first surface of said first stacked substrate, said first semiconductor die connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a second stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a second semiconductor die disposed on said first surface of said second stacked substrate, said second semiconductor die connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a third semiconductor die disposed on said second surface of said second stacked substrate; a first plurality of connections connecting said base substrate and said first stacked substrate, at least one connection of said first plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of the plurality of bond pads on the first surface of said first stacked substrate; a second plurality of connections connecting said second stacked substrate and said first stacked substrate, at least one connection of said second plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of the plurality of bond pads on the second surface of said first stacked substrate; a third stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said third stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; a fourth semiconductor die disposed on said second surface of said third stacked substrate; a fifth semiconductor die disposed on said first surface of said third stacked substrate, said fifth semiconductor die connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; and a third plurality of connections connecting said third stacked substrate and said second stacked substrate, at least one connection of said third plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of the plurality of bond pads on the first surface of said second stacked substrate.

Claim 13

A semiconductor assembly comprising: a base substrate having a first surface including a plurality of bonds pads thereon, a second surface including a plurality of bond pads thereon, and a plurality of traces, at least one trace of said plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of said plurality of bond pads on said second surface of said base substrate; a first stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said first stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a first semiconductor die disposed on said first surface of said first stacked substrate, said first semiconductor die connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a second stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a second semiconductor die disposed on said first surface of said second stacked substrate, said second semiconductor die connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a third semiconductor die disposed on said second surface of said second stacked substrate; a first plurality of connections connecting said base substrate and said first stacked substrate, at least one connection of said first plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of the plurality of bond pads on the first surface of said first stacked substrate; a second plurality of connections connecting said second stacked substrate and said first stacked substrate, at least one connection of said second plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of the plurality of bond pads on the second surface of said first stacked substrate; a third stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said third stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; a fourth semiconductor die disposed on said second surface of said third stacked substrate; a fifth semiconductor die disposed on said first surface of said third stacked substrate, said fifth semiconductor die connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; and a third plurality of connections connecting said third stacked substrate and said second stacked substrate, at least one connection of said third plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of the plurality of bond pads on the first surface of said second stacked substrate.

Claim 14

The semiconductor assembly of claim 11 , wherein said first plurality of connections connecting said base substrate and said first stacked substrate support said first stacked substrate.

Claim 15

The semiconductor assembly of claim 11 , wherein said second plurality of connections extending connecting said first stacked substrate and said second stacked substrate support said second stacked substrate.

Claim 16

The semiconductor assembly of claim 11 , wherein said first plurality of connections includes solder, conductive adhesives, Z-axis conductive material, flex-contacts, spring contacts, wire bonds, and TAB tape.

Claim 17

The semiconductor assembly of claim 11 , wherein said second plurality of connections includes solder, conductive adhesives, Z-axis conductive material, flex-contacts, spring contacts, wire bonds, and TAB tape.

Claim 18

The semiconductor assembly of claim 11 , said assembly further comprising: a fourth plurality of connections, at least one connection of said third plurality of connections connecting said at least one bond pad of said plurality of bond pads on said second surface of said base substrate to external electrical circuitry.

Claim 19

The semiconductor assembly of claim 11 , wherein said first semiconductor die disposed on said first surface of said first stacked substrate is connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate through flip chip attachment, wirebonding, TAB tape, or a combination thereof.

Claim 20

The semiconductor assembly of claim 11 , wherein said second semiconductor die disposed on said first surface of said second stacked substrate is connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate through flip chip attachment, wirebonding, TAB tape, or a combination thereof.

Claim 21

The semiconductor assembly of claim 11 , wherein said third semiconductor die disposed on said second surface of said second stacked substrate is connected to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate.

Claim 22

The semiconductor assembly of claim 11 , wherein said third semiconductor die disposed on said second surface of said second stacked substrate is connected to at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate.

Claim 23

The semiconductor assembly of claim 11 , wherein said second semiconductor die disposed on said first surface of said second stacked substrate is connected to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate and wherein said third semiconductor die disposed on said second surface of said second stacked substrate is connected to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate.

Claim 24

The semiconductor assembly of claim 11 , further comprising: a fourth stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said fourth stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said fourth stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said fourth stacked substrate, said fourth stacked substrate located above said second stacked substrate, said fourth stacked substrate having a size less than the base substrate, the first stacked substrate, the second stacked substrate, and the third stacked substrate; a sixth semiconductor die disposed on said first surface of said fourth stacked substrate, said sixth semiconductor die connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said fourth stacked substrate; and a fourth plurality of connections connecting said fourth stacked substrate and said second stacked substrate, at least one connection of said fourth plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said fourth stacked substrate to at least one bond pad of the plurality of bond pads on the first surface of said second stacked substrate.

Claim 25

A semiconductor assembly comprising: a base substrate having a first surface including a plurality of bonds pads thereon, a second surface including a plurality of bond pads thereon, and a plurality of traces, at least one trace of said plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of said plurality of bond pads on said second surface of said base substrate; a first stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said first stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a plurality of first semiconductor dice disposed on said first surface of said first stacked substrate, each die of said plurality of first semiconductor dice connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a second stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a plurality of second semiconductor dice disposed on said first surface of said second stacked substrate, each die of said plurality of second semiconductor dice connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a plurality of third semiconductor dice disposed on said second surface of said second stacked substrate; a first plurality of connections connecting said base substrate and said first stacked substrate, at least one connection of said first plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of the plurality of bond pads on the first surface of said first stacked substrate; a second plurality of connections connecting said second stacked substrate and said first stacked substrate, at least one connection of said second plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of the plurality of bond pads on the second surface of said first stacked substrate; a third stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said third stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; a plurality of fourth semiconductor dice disposed on said first surface of said third stacked substrate, each die of said third plurality of third semiconductor dice connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; a plurality of fifth semiconductor dice disposed on said second surface of said third stacked substrate; and a third plurality of connections connecting said third stacked substrate and said second stacked substrate, at least one connection of said third plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of the plurality of bond pads on the first surface of said second stacked substrate.

Claim 26

A semiconductor assembly comprising: a base substrate having a first surface including a plurality of bonds pads thereon, a second surface including a plurality of bond pads thereon, and a plurality of traces, at least one trace of said plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of said plurality of bond pads on said second surface of said base substrate; a first stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said first stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a plurality of first semiconductor dice disposed on said first surface of said first stacked substrate, each die of said plurality of first semiconductor dice connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate; a second stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a plurality of second semiconductor dice disposed on said first surface of said second stacked substrate, each die of said plurality of second semiconductor dice connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate; a plurality of third semiconductor dice disposed on said second surface of said second stacked substrate; a first plurality of connections connecting said base substrate and said first stacked substrate, at least one connection of said first plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said base substrate to at least one bond pad of the plurality of bond pads on the first surface of said first stacked substrate; a second plurality of connections connecting said second stacked substrate and said first stacked substrate, at least one connection of said second plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of the plurality of bond pads on the second surface of said first stacked substrate; a third stacked substrate having a first surface including a plurality of bond pads thereon, a second surface including a plurality of bond pads thereon, a first plurality of traces, at least one trace of said first plurality of traces connecting at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said third stacked substrate, and a second plurality of traces, at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; a plurality of fourth semiconductor dice disposed on said first surface of said third stacked substrate, each die of said third plurality of third semiconductor dice connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said third stacked substrate; a plurality of fifth semiconductor dice disposed on said second surface of said third stacked substrate; and a third plurality of connections connecting said third stacked substrate and said second stacked substrate, at least one connection of said third plurality of connections connecting said at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate to at least one bond pad of the plurality of bond pads on the first surface of said second stacked substrate.

Claim 27

The semiconductor assembly of claim 23 , wherein said first plurality of connections connecting said base substrate and said first stacked substrate support said first stacked substrate.

Claim 28

The semiconductor assembly of claim 23 , wherein said second plurality of connections connecting said first stacked substrate and said second stacked substrate support said second stacked substrate.

Claim 29

The semiconductor assembly of claim 23 , wherein said first plurality of connections includes solder, conductive adhesives, Z-axis conductive material, flex-contacts, spring contacts, wire bonds, and TAB tape.

Claim 30

The semiconductor assembly of claim 23 , wherein said second plurality of connections includes solder, conductive adhesives, Z-axis conductive material, flex-contacts, spring contacts, wire bonds, and TAB tape.

Claim 31

The semiconductor assembly of claim 23 , said assembly further comprising: a third plurality of connections, at least one connection of said third plurality of connections connecting said at least one bond pad of said plurality of bond pads on said second surface of said base substrate to external electrical circuitry.

Claim 32

The semiconductor assembly of claim 23 , wherein each die of said first plurality of semiconductor dice disposed on said first surface of said first stacked substrate is connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said first stacked substrate through one of flip chip attachment, wirebonding, TAB tape, or a combination thereof.

Claim 33

The semiconductor assembly of claim 23 , wherein said each die of said second plurality of semiconductor dice disposed on said first surface of said second stacked substrate is connected to said at least one trace of said second plurality of traces connected to another bond pad of said plurality of bond pads on said first surface of said second stacked substrate through one of flip chip attachment, wirebonding, TAB tape, or a combination thereof.

Claim 34

The semiconductor assembly of claim 23 , further comprising: a second semiconductor die disposed on said second surface of said first stacked substrate, said second semiconductor die connected to at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate.

Claim 35

The semiconductor assembly of claim 23 , further comprising: a second semiconductor die disposed on said second surface of said first stacked substrate, said second semiconductor die connected to at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate; and a third semiconductor die disposed on said second surface of said second stacked substrate, said third semiconductor die connected to at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate.