Layered features for co-fired module integration

Claim 2

A unitized multilayer circuit structure comprising: a plurality of planar dielectric insulating layers stacked in laminar fashion and integrally fused to form a unitized multilayer substrate having sides formed by edges of the dielectric insulating layers; and a recess formed respectively in one side of and opposite side of said substrate and extending partially into said substrate; whereby the unitized multilayer circuit structure is secured to a higher level assembly by engagement of said recess by a fastener.

Claim 3

The unitized multilayer circuit structure of claim 1 wherein said recess is comprised of respective openings along edges of a plurality of contiguous ones of said plurality of dielectric insulating layers.

Claim 4

A unitized multilayer circuit structure comprising: a first plurality of planar dielectric insulating layers stacked in laminar fashion and integrally fused to form a first unitized multilayer substrate having sides formed by edges of the dielectric insulating layers, said substrate having a top and a bottom; a second plurality of planar dielectric insulating layers stacked in laminar fashion and integrally fused to form a second unitized multilayer substrate having sides formed by edges of the dielectric insulating layers, said substrate having a top and a bottom; said first unitized multilayer substrate and said second unitized multilayer substrate being positioned such that a first side of said first unitized multilayer substrate is opposite a first side of said second unitized multilayer substrate; a recess formed in said first side of said first unitized multilayer substrate, said recess extending into said first unitized multilayer substrate and being comprised of respective openings along edges of a plurality of contiguous ones of said first plurality of dielectric insulating layers; a recess formed in said first side of said second unitized multilayer substrate, said recess extending into said second unitized multilayer substrate and being comprised of respective openings along edges of a plurality of contiguous ones of said second plurality of dielectric insulating layers; and fastening means engaged in said recess formed in said first side of said first unitized multilayer substrate and said recess formed in said first side of said second unitized multilayer substrate for securing said first unitized multilayer substrate and said second unitized multilayer substrate to an assembly.

Claim 5

A unitized multilayer circuit structure comprising: a first plurality of planar dielectric insulating layers stacked in laminar fashion and integrally fused to form a first unitized multilayer substrate having sides formed by edges of the dielectric insulating layers, said substrate having a top and a bottom; a second plurality of planar dielectric insulating layers stacked in laminar fashion and integrally fused to form a second unitized multilayer substrate having sides formed by edges of the dielectric insulating layers, said substrate having a top and a bottom; said first unitized multilayer substrate and said second unitized multilayer substrate being positioned such that a first side of said first unitized multilayer substrate is opposite a first side of said second unitized multilayer substrate; a recess formed in said first side of said first unitized multilayer substrate, said recess extending into said first unitized multilayer substrate and being comprised of respective openings along edges of a plurality of contiguous ones of said first plurality of dielectric insulating layers; a recess formed in said first side of said second unitized multilayer substrate, said recess extending into said second unitized multilayer substrate and being comprised of respective openings along edges of a plurality of contiguous ones of said second plurality of dielectric insulating layers; and fastening means engaged in said recess formed in said first side of said first unitized multilayer substrate and said recess formed in said first side of said second unitized multilayer substrate for securing said first unitized multilayer substrate and said second unitized multilayer substrate to an assembly.

Claim 6

The unitized multilayer circuit structure of claim 3 further including: a step formed in the top of said first substrate adjacent said first side of said first substrate; a step formed in the top of said second substrate adjacent one side of said first substrate and facing said step formed in the top of said first substrate; and a cover spanning said step formed in the top of said first substrate and said step formed in the top of said second substrate.