Method of packaging and powering integrated circuit chips and the chip assembly formed thereby

Claim 2

An IC chip assembly comprising a chip having an array of exposed contacts at a face thereof; a substrate having an array of exposed contacts at a face thereof; interposer means positioned between said chip and substrate, said interposer means including electrically insulating compliant means for providing compliance between said chip and said substrate, said compliant means having first and second opposite surfaces which face said chip and substrate respectively, first exposed contacts at said first surface of the compliant means which engage the contacts on the chip, and second exposed contacts at said second surface of the compliant means which engage the contacts of the substrate; connecting means electrically connecting said first and second contacts; thermal transfer means engaging the face of said chip opposite said first face thereof; and compressing means for compressing said interposer means between said substrate and said thermal transfer means, said interposer means thereby simultaneously providing compliance between said chip and substrate, establishing relatively low inductance electrical connections between the array of chip contacts and the array of substrate contacts and good thermal contact between said chip and said thermal transfer means.

Claim 3

The chip assembly defined in claim 1 wherein the contacts of said chip are contact bumps raised from said chip first face, and said first contacts of the interposer means are relatively flat pads which are engaged by said bumps.

Claim 4

The chip assembly defined in claim 2 wherein said connecting means comprise conductors extending through said compliant means between selected first and second contacts thereon.

Claim 5

The chip assembly defined in claim 3 wherein each first contact is cantilevered from its said conductor and is engaged by a said chip contact bump at a location offset along said contact from that conductor to provide a compliant connection between said conductor and said chip bump.

Claim 6

The chip assembly defined in claim 3 wherein each second contact is cantilevered from its said conductor and is engaged by a substrate contact at a location offset along said second contact from that conductor to provide a compliant connection between said conductor and said substrate contact.

Claim 7

The chip assembly defined in claim 3 wherein said contacts are of gold or other relatively inert metal.

Claim 8

The chip assembly defined in claim 2 wherein said compliant means are of Viton fluoroelastomer or silicone rubber.

Claim 9

The chip assembly defined in claim 3 wherein said conductors are plated vias extending through said compliant means between said first and second contacts thereon.

Claim 10

The circuit chip assembly defined in claim 1 wherein the contacts on the chip are relatively flat pads and said first contacts on the interposer means have bumps which engage said pads.

Claim 11

The chip assembly defined in claim 9 wherein said conductors comprise bundles of tiny electrically conductive strands embedded in said compliant means and whose opposite ends are exposed at the first and second faces of said compliant means.

Claim 12

The chip assembly defined in claim 1 wherein said thermal transfer means comprises a heat-sink cover member which overlies and protectively encloses said chip, said interposer means and the contacts thereon, and means for securing together said member and said substrate.

Claim 13

The chip assembly defined in claim 1 wherein said thermal transfer means comprise a compliant pad and a multiplicity, of thermally conductive strands embedded in said pad throughout substantially its entire extent.

Claim 14

The circuit chip assembly defined in claim 12 and further including a heat-sink cover member which overlies and protectively encloses said chip, said interposer means and said compliant pad.

Claim 15

The circuit chip assembly defined in claim 1 wherein the contact array on said chip is spaced from the periphery of said chip first face; and further including additional chip contacts exposed at said chip first face, additional substrate contacts exposed at said substrate face, and a flexible circuit lead frame mechanically and electrically attached at a first end thereof to said additional chip contacts and at a second and thereof to said additional substrate contacts.

Claim 16

The chip assembly defined in claim 14 wherein said chip and said lead frame form a TAB-type integrated circuit.

Claim 17

The chip assembly defined in claim 14 wherein at least one of said pad first contacts and said pad second contacts are connected electrically but not mechanically to the contacts with which they are engaged.

Claim 18

The chip assembly defined in claim 14 wherein the contacts in said array of contacts on said chip include power contacts therefor, and said additional chip contacts include signal contacts therefor.

Claim 19

An IC chip assembly comprising a chip having an array of exposed contacts at the periphery of a first face thereof and additional chip contacts exposed at said chip first face; a substrate having an array of exposed contacts at a face thereof and additional substrate contacts at said substrate face; interposer means positioned between said chip and substrate, said interposer means including electrically insulating compliant means for providing compliance between said chip and said substrate, said compliant means having first and second opposite surfaces which face said chip and substrate respectively, first exposed contacts at said first surface of the compliant means which engage the said additional contacts of the chip, and second exposed contacts at said second surface of the compliant means which engage said additional contacts of the substrate; connecting means electrically connecting said first and second contacts; a flexible circuit lead frame mechanically and electrically attached at a first electrical end thereof to said array of chip contacts, and at a second electrical end thereof to said array of substrate contacts; and means for engaging said chip, interposer means and substrate together so that said interposer means provides compliance between said chip and said substrate and establishes relatively low inductance electrical connections between said additional contacts of said chip and said substrate.

Claim 20

An IC chip assembly comprising a chip having an array of exposed contacts at the periphery of a first face thereof and additional chip contacts exposed at said chip first face; a substrate having an array of exposed contacts at a face thereof and additional substrate contacts at said substrate face; interposer means positioned between said chip and substrate, said interposer means including electrically insulating compliant means for providing compliance between said chip and said substrate, said compliant means having first and second opposite surfaces which face said chip and substrate respectively, first exposed contacts at said first surface of the compliant means which engage the said additional contacts of the chip, and second exposed contacts at said second surface of the compliant means which engage said additional contacts of the substrate; connecting means electrically connecting said first and second contacts; a flexible circuit lead frame mechanically and electrically attached at a first electrical end thereof to said array of chip contacts, and at a second electrical end thereof to said array of substrate contacts; and means for engaging said chip, interposer means and substrate together so that said interposer means provides compliance between said chip and said substrate and establishes relatively low inductance electrical connections between said additional contacts of said chip and said substrate.

Claim 21

The chip assembly defined in claim 18 wherein said chip and said lead frame form a TAB-type integrated circuit.

Claim 22

The chip assembly defined in claim 18 wherein at least one of said first contacts and said second contacts are connected electrically but not mechanically to the contacts with which they are engaged.

Claim 23

The chip assembly defined in claim 18 wherein the contacts in said array of contacts on said chip include power contacts therefor, and said additional chip contacts include signal contacts therefor.

Claim 24

The chip assembly defined in claim 18 wherein said connecting means are included in said interposer means.

Claim 25

The chip assembly defined in claim 18 wherein said compliant means consist of a resilient dielectric pad sandwiched between said chip and said substrate.

Claim 26

An IC chip assembly comprising a chip having an array of exposed contacts at the periphery of a first face thereof and additional chip contacts exposed at said chip first face; a substrate having an array of exposed contacts at a face thereof and additional substrate contacts exposed at said substrate face; interposer means located between said chip and said substrate, said interposer means including first compliant contacts engaging said additional chip contacts, second compliant contacts engaging said additional substrate contacts and conductors electrically connecting selected ones of said first and second contacts; a lead frame mechanically and electrically connected at a first electrical end thereof to said array of chip contacts, and at a second electrical end thereof to said array of substrate contacts; heat sink means engaging the face of said chip opposite said first face thereof; and means for engaging said chip, interposer means, substrate and heat sink means together so that said interposer means simultaneously provides compliance between said chip and said substrate and establishes relatively low inductance electrical connections between said additional chip and substrate contacts and good thermal contact between said chip and said heat sink means.

Claim 27

An IC chip assembly comprising a chip having an array of exposed contacts at the periphery of a first face thereof and additional chip contacts exposed at said chip first face; a substrate having an array of exposed contacts at a face thereof and additional substrate contacts exposed at said substrate face; interposer means located between said chip and said substrate, said interposer means including first compliant contacts engaging said additional chip contacts, second compliant contacts engaging said additional substrate contacts and conductors electrically connecting selected ones of said first and second contacts; a lead frame mechanically and electrically connected at a first electrical end thereof to said array of chip contacts, and at a second electrical end thereof to said array of substrate contacts; heat sink means engaging the face of said chip opposite said first face thereof; and means for engaging said chip, interposer means, substrate and heat sink means together so that said interposer means simultaneously provides compliance between said chip and said substrate and establishes relatively low inductance electrical connections between said additional chip and substrate contacts and good thermal contact between said chip and said heat sink means.