Patent US4807766A successfully refreshed from Google Patents.
US6950340B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asymmetric band-gap engineered nonvolatile memory device
Assignee: Micron Technology Inc
•
Filing: 2004-08-10
•
Granted: 2005-09-27
•
Expires: 2024-08-10
Abstract
Abstract Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source/drain regions separated by a channel region in a substrate, a control gate, and a gate stack between the control gate and the channel region. The gate stack includes a first insulator region in contact with the channel region, a floating charge-storage region in contact with the first insulator region, and a second insulator region in contact with the floating charge-storage region and the control gate. The gate stack includes selected material, in conjunction with control gate metallurgy, for providing desired asymmetric energy barriers that are adapted to primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and to retain a programmed charge in the floating charge-storage region. Other aspects are provided herein.
Inventors
- 👤 Arup Bhattacharyya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:55
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10D30/6893; H10D30/69; H10D30/694; H10D30/697; H10D64/00; H10D64/01; H10D64/031; H10D64/035; G11C16/04; G11C16/0408; G11C16/0416
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
224 words
A method for operating a plurality of adjacent nonvolatile memory cells, comprising: simultaneously erasing the plurality of nonvolatile memory cells from the high threshold nonconducting state (1) to the low threshold conducting state (0) by applying a positive programming pulse to a plurality of control gates of the plurality of adjacent nonvolatile memory cells while pulling a substrate common to all of the plurality of adjacent nonvolatile memory cells to a ground potential, wherein the positive programming pulse induces an erase primary charge transport of holes from the control gate to a floating charge-storage region of each of the cells; and simultaneously writing the plurality of nonvolatile memory cells from a low threshold conducting state (0) to a high threshold nonconducting state (1) by tying the substrate common to all of the plurality of adjacent nonvolatile memory cells to a plurality of drain nodes of the plurality of adjacent nonvolatile memory cells and applying a positive programming pulse to the drain nodes to capacitively pull the substrate of the plurality of cells to a positive potential while pulling the control gate of the cells to be written to a ground potential, wherein the positive programming pulse induces a write primary charge transport of holes from the floating charge-storage region of the plurality of cells to the control gate of the cells to be written.
Claim 2
Independent Claim
224 words
A method for operating a plurality of adjacent nonvolatile memory cells, comprising: simultaneously erasing the plurality of nonvolatile memory cells from the high threshold nonconducting state (1) to the low threshold conducting state (0) by applying a positive programming pulse to a plurality of control gates of the plurality of adjacent nonvolatile memory cells while pulling a substrate common to all of the plurality of adjacent nonvolatile memory cells to a ground potential, wherein the positive programming pulse induces an erase primary charge transport of holes from the control gate to a floating charge-storage region of each of the cells; and simultaneously writing the plurality of nonvolatile memory cells from a low threshold conducting state (0) to a high threshold nonconducting state (1) by tying the substrate common to all of the plurality of adjacent nonvolatile memory cells to a plurality of drain nodes of the plurality of adjacent nonvolatile memory cells and applying a positive programming pulse to the drain nodes to capacitively pull the substrate of the plurality of cells to a positive potential while pulling the control gate of the cells to be written to a ground potential, wherein the positive programming pulse induces a write primary charge transport of holes from the floating charge-storage region of the plurality of cells to the control gate of the cells to be written.
Claim 3
Dependent Claim
64 words
The method of claim 1 , wherein both the positive programming pulse applied at the control gates to erase the nonvolatile memory cell and the positive programming pulse applied at the drain nodes to write the nonvolatile memory cells includes a 10 msec. potential having a voltage calculated to provide an electric field of approximately 12E6 V/cm between the control gate and the substrate.
Claim 4
Dependent Claim
71 words
The method of claim 1 , wherein both the positive programming pulse applied at the control gates to erase the nonvolatile memory cells and the positive programming pulse applied at the drain nodes to write the nonvolatile memory cells includes a 10 msec. potential having a voltage calculated to provide an electric field within a range of approximately 6E6 V/cm to approximately 7E6 V/cm between the control gates and the substrate.
Claim 5
Dependent Claim
112 words
The method of claim 1 , wherein both the positive programming pulse applied at the control gates to erase the nonvolatile memory cells and the positive programming pulse applied at the drain nodes to write the nonvolatile memory cells includes a 10 msec. potential having a voltage calculated to provide an electric field of approximately 4E6 V/cm between the control gate and the substrate, and wherein the positive programming pulse induces a write primary charge transport of holes from the floating charge-storage region of the plurality of cells through an injector layer of silicon rich nitride having an index of refraction greater than approximately 2.30 to the control gate of the cells.
Claim 6
Dependent Claim
203 words
The method of claim 1 , wherein both the positive programming pulse applied at the control gates to erase the nonvolatile memory cells and the positive programming pulse applied at the drain nodes to write the nonvolatile memory cells includes a 10 msec. potential having a voltage calculated to provide an electric field of approximately 3.5E6 V/cm between the control gate and the substrate, and wherein the positive programming pulse induces a write primary charge transport of holes from the floating charge-storage region of the plurality of cells through an injector layer of silicon rich nitride having an index of refraction greater than approximately 2.30 to the control gate of the cells and a complimentary charge transport of electrons from the control gate of the cells to the floating gate through the injector layer of silicon rich nitride, and wherein the positive programming pulse induces a write secondary charge transport of electrons from the floating charge-storage region of the plurality of cells through a tunneling layer and through an injector layer of silicon rich nitride having an index of refraction greater than approximately 2.30 to an oxide layer between the floating charge-storage region and a channel region of the substrate of the cells.
Claim 7
Independent Claim
320 words
A method for operating a memory array of nonvolatile memory cells, where the memory cells are arranged in a first plurality of rows and a second plurality of columns, each of the memory cells has at least a drain region, a source region, a channel region, a floating gate, a control gate and a backgate, all of the control gates of the memory cells in at least one of the first plurality of rows are connected to a common word line, all of the drain regions of the memory cells in at least one of the second plurality of columns are connected to a common bit line, and all of the backgates of the memory cells in at least one of the first plurality of rows and in at least one of the second plurality of columns are connected to a common backgate line, the method comprising: selecting at least one memory cell for erasing from the high threshold nonconducting state (1) to the low threshold conducting state (0) by applying a positive programming pulse to a selected word line while the source line, the backgate line and the bit line of the memory cells are connected to a reference potential; selecting at least one memory cell for writing from a low threshold conducting state (0) to a high threshold nonconducting state (1) by applying a positive programming pulse to a selected bit line while letting the backgate line float and connecting a selected source line and word line to a reference potential; and selecting at least one memory cell for reading by applying a positive reading pulse to a selected bit line and word line while connecting a selected source line and the backgate line to a reference potential, and sensing a current on the bit line to determine if the selected cell is in a conducting low threshold state (0) or in a nonconducting high threshold state (1).
Claim 8
Independent Claim
320 words
A method for operating a memory array of nonvolatile memory cells, where the memory cells are arranged in a first plurality of rows and a second plurality of columns, each of the memory cells has at least a drain region, a source region, a channel region, a floating gate, a control gate and a backgate, all of the control gates of the memory cells in at least one of the first plurality of rows are connected to a common word line, all of the drain regions of the memory cells in at least one of the second plurality of columns are connected to a common bit line, and all of the backgates of the memory cells in at least one of the first plurality of rows and in at least one of the second plurality of columns are connected to a common backgate line, the method comprising: selecting at least one memory cell for erasing from the high threshold nonconducting state (1) to the low threshold conducting state (0) by applying a positive programming pulse to a selected word line while the source line, the backgate line and the bit line of the memory cells are connected to a reference potential; selecting at least one memory cell for writing from a low threshold conducting state (0) to a high threshold nonconducting state (1) by applying a positive programming pulse to a selected bit line while letting the backgate line float and connecting a selected source line and word line to a reference potential; and selecting at least one memory cell for reading by applying a positive reading pulse to a selected bit line and word line while connecting a selected source line and the backgate line to a reference potential, and sensing a current on the bit line to determine if the selected cell is in a conducting low threshold state (0) or in a nonconducting high threshold state (1).
Claim 9
Dependent Claim
27 words
The method of claim 6 , wherein the reading of the nonvolatile memory cell by applying the positive reading pulse comprises a pulse of approximately 2.5 V.
Claim 10
Dependent Claim
14 words
The method of claim 6 , wherein the reference voltage is a ground potential.
Claim 11
Dependent Claim
56 words
The method of claim 6 , wherein both the positive programming pulse applied to erase the nonvolatile memory array and the positive programming pulse applied to write the nonvolatile memory array includes a 10 msec. potential having a voltage calculated to provide an electric field of approximately 12E6 V/cm between the control gate and the substrate.
Claim 12
Dependent Claim
65 words
The method of claim 6 , wherein both the positive programming pulse applied to erase the nonvolatile memory array cells and the positive programming pulse applied to write the nonvolatile memory array cells includes a 10 msec. potential having a voltage calculated to provide an electric field within a range of approximately 6E6 V/cm to approximately 7E6 V/cm between the control gates and the substrate.
Claim 13
Dependent Claim
105 words
The method of claim 6 , wherein both the positive programming pulse applied to erase the nonvolatile memory array cells and the positive programming pulse applied to write the nonvolatile memory array cells includes a 10 msec. potential having a voltage calculated to provide an electric field of approximately 4E6 V/cm between the control gate and the backgate, and wherein the positive programming pulse induces a write primary charge transport of holes from the floating charge-storage region of the plurality of cells through an injector layer of silicon rich nitride having an index of refraction greater than 2.30 to the control gate of the cells.
Claim 14
Dependent Claim
194 words
The method of claim 6 , wherein both the positive programming pulse applied to erase the nonvolatile memory array cells and the positive programming pulse applied to write the nonvolatile memory array cells includes a 10 msec. potential having a voltage calculated to provide an electric field of approximately 3.5E6 V/cm between the control gate and the substrate, and wherein the positive programming pulse induces a write primary charge transport of holes from the floating charge-storage region of the plurality of cells through an injector layer of silicon rich nitride having an index of refraction greater than 2.30 to the control gate of the cells, a complimentary charge transport of electrons from the control gate of the cells to the floating gate through the injector layer of silicon rich nitride, and wherein the positive programming pulse induces a write primary charge transport of electrons from the floating charge-storage region of the plurality of cells through a tunneling layer and through an injector layer of silicon rich nitride having an index of refraction greater than 2.30 to an oxide layer between the floating charge-storage region and a channel region of the substrate of the cells.
Claim 15
Dependent Claim
51 words
The method of claim 6 , further comprising reading the nonvolatile memory cell by applying the positive reading pulse to a selected bit line and word line while connecting a selected source line and the substrate to a reference potential, the reading pulse having a positive potential of approximately 2.5 V.
Claim 16
Independent Claim
301 words
A method for operating a nonvolatile memory cell that includes a control gate and further includes a gate stack including a Silicon Dioxide (SiO 2 ) layer in contact with a channel region of the memory cell; a Tantalum Oxide (Ta 2 O 5 ) layer in contact with the SiO 2 layer; a charge-storage region in contact with the Ta 2 O 5 layer, and a Zirconium Oxide (ZrO 2 ) layer in contact with the charge-storage layer, the method comprising: erasing the nonvolatile memory cell from the high threshold nonconducting state to the low threshold conducting state, including applying a first programming pulse to the control gate of the cell while pulling a substrate of the cell to a first reference potential, wherein the first programming pulse induces an erase primary charge transport of holes from the control gate through the ZrO 2 layer to the charge-storage region and a complimentary erase charge transport of electrons from the charge-storage region through the ZrO 2 layer to the control gate; writing the nonvolatile memory cell from the low threshold conducting state to the high threshold nonconducting state, including applying a second programming pulse to a drain node of the cell to capacitively pull the substrate of the cell to a desired potential while pulling the control gate of the cell to a second reference potential, wherein the second programming pulse induces a write primary charge transport of holes from the charge-storage region through the ZrO 2 layer to the control gate and a complimentary write charge transport of electrons from the control gate through the ZrO 2 layer to the charge-storage region; and reading the nonvolatile cell, including sensing drain current to determine if the memory cell is in the low threshold conducting state or the high threshold nonconducting state.
Claim 17
Independent Claim
301 words
A method for operating a nonvolatile memory cell that includes a control gate and further includes a gate stack including a Silicon Dioxide (SiO 2 ) layer in contact with a channel region of the memory cell; a Tantalum Oxide (Ta 2 O 5 ) layer in contact with the SiO 2 layer; a charge-storage region in contact with the Ta 2 O 5 layer, and a Zirconium Oxide (ZrO 2 ) layer in contact with the charge-storage layer, the method comprising: erasing the nonvolatile memory cell from the high threshold nonconducting state to the low threshold conducting state, including applying a first programming pulse to the control gate of the cell while pulling a substrate of the cell to a first reference potential, wherein the first programming pulse induces an erase primary charge transport of holes from the control gate through the ZrO 2 layer to the charge-storage region and a complimentary erase charge transport of electrons from the charge-storage region through the ZrO 2 layer to the control gate; writing the nonvolatile memory cell from the low threshold conducting state to the high threshold nonconducting state, including applying a second programming pulse to a drain node of the cell to capacitively pull the substrate of the cell to a desired potential while pulling the control gate of the cell to a second reference potential, wherein the second programming pulse induces a write primary charge transport of holes from the charge-storage region through the ZrO 2 layer to the control gate and a complimentary write charge transport of electrons from the control gate through the ZrO 2 layer to the charge-storage region; and reading the nonvolatile cell, including sensing drain current to determine if the memory cell is in the low threshold conducting state or the high threshold nonconducting state.
Claim 18
Dependent Claim
28 words
The method of claim 14 , wherein the first and second reference potentials are the same potential, and the first and second programming pulses are the same potential.
Claim 19
Dependent Claim
26 words
The method of claim 15 , wherein the first and second reference potentials are ground, and the first and second programming pulses are a positive potential.
Claim 20
Dependent Claim
24 words
The method of claim 14 , wherein both erasing and writing include applying a programming field of approximately 12E6 V/cm across the gate stack.
Claim 21
Dependent Claim
31 words
The method of claim 14 , wherein both erasing and writing include applying a programming field within a range between approximately 6E6 V/cm and approximately 7E6 V/cm across the gate stack.
Claim 22
Dependent Claim
24 words
The method of claim 14 , wherein both erasing and writing include applying a programming field of approximately 4E6 V/cm across the gate stack.
Claim 23
Dependent Claim
24 words
The method of claim 14 , wherein both erasing and writing include applying a programming field of approximately 3.5E6 V/cm across the gate stack.
References Cited (Backward Citations)
US3978577A
Cited
US4412902A
Cited
US4495219A
Cited
US4449205A
Cited
US4717943A
Cited
US4794565A
Cited
US4780424A
Cited
US4870470A
Cited
US5043946A
Cited
US5350738A
Cited
US5646430A
Cited
US5332915A
Cited
US5617351A
Cited
US5600592A
Cited
US5557569A
Cited
US5498558A
Cited
US5510278A
Cited
US5455792A
Cited
US5445984A
Cited
US6172397B1
Cited
US5691230A
Cited
US5963476A
Cited
US5801993A
Cited
US5923056A
Cited
US5952692A
Cited
US5852306A
Cited
US5801401A
Cited
US5880991A
Cited
US5936274A
Cited
US6238976B1
Cited
US6143636A
Cited
US6307775B1
Cited
US6249020B1
Cited
US6031263A
Cited
US6246606B1
Cited
US6351411B2
Cited
US6069816A
Cited
US6124729A
Cited
US6153468A
Cited
US5991225A
Cited
US6229175B1
Cited
US6101131A
Cited
US6025627A
Cited
US5981350A
Cited
US6169306B1
Cited
US6208164B1
Cited
US6134175A
Cited
US6163049A
Cited
US6127227A
Cited
US6740928B2
Cited
US6288419B1
Cited
US6141238A
Cited
US20010013621A1
Cited
US6249460B1
Cited
US6444545B1
Cited
US6424001B1
Cited
US6475857B1
Cited
US20030042527A1
Cited
US20030048666A1
Cited
US20030043633A1
Cited
US20030043637A1
Cited
US20030042532A1
Cited
US20030043632A1
Cited
US20030043630A1
Cited
US20030043622A1
Cited
US6586797B2
Cited
US6778441B2
Cited
US20030045082A1
Cited
US6743681B2
Cited
US20040004247A1
Cited
US20040004245A1
Cited
US20040004859A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-09-26 | 2009-03-28 | 2009-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-09-26 | 2013-03-28 | 2013-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-09-26 | 2017-03-28 | 2017-09-27 | $7700.00 | Window Closed / Lapsed |