Low voltage flash EEPROM C-cell using fowler-nordheim tunneling

Claim 2

An electrically programmable, non-volatile memory cell arrangement, in a semiconductor substrate, comprising: a first doped region in said substrate of a first conductivity type, having a central portion, and first, second, third and fourth source/drain portions extending outwardly from said central portion; second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first, second, third and fourth source/drain portions, respectively; a first floating gate structure and a second floating gate structure disposed on top of said channels formed between said first source/drain portion and said second doped region, and said second source/drain portion and said third doped region, respectively, and a first control gate structure and a second control gate structure disposed on top of said first and said second floating gate structures, respectively, forming a first storage transistor and a second storage transistor operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and a third and a fourth floating gate structure disposed on top of said channels formed between said third source/drain portion and said fourth doped region, and said fourth source/drain portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming a third storage transistor and a fourth storage transistor operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said third source/drain portion and said fourth source/drain portion, respectively.

Claim 3

A memory cell arrangement according to claim 1, wherein said first, second, third and fourth storage transistors are operable to be programmed by Fowler-Nordheim tunneling from only one side by having a reach-through region formed on only said one side, at which said Fowler-Nordheim tunneling occurs.

Claim 4

A memory cell arrangement according to claim 2, wherein said reach-through region comprises an extension of said third source/drain portion and said fourth source/drain portion under said third floating gate structure and said fourth floating gate structure, respectively, and further comprises an extension of said second doped region and said third doped region under said first floating gate structure and said second floating gate structure.

Claim 5

A memory cell arrangement according to claim 1, wherein said central portion of said first doped region is substantially rectangular in configuration with the source/drain regions extending from the corners thereof.

Claim 6

An electrically programmable, non-volatile memory cell array, in a semiconductor substrate, comprising a plurality of memory cell arrangements, each of said arrangements comprising: a first doped region in said substrate of a first conductivity type, having a central portion, and first, second, third and fourth source/drain portions extending outwardly from said central portion; second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first, second, third and fourth source/drain portions, respectively; a first and a second floating gate structure disposed on top of said channels formed between said first source/drain portion and said second doped region, and said second source/drain portion and said third doped region, respectively, and first and second control gate structures disposed on top of said first and said second floating gate structures, respectively, forming first and second storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and a third and a fourth floating gate structure disposed on top of said channels formed between said third source/drain portion and said fourth doped region, and said fourth source/drain portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming third and fourth storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said third source/drain portion and said fourth source/drain portion, respectively; wherein said memory cell arrangements are arranged in an array and interconnected such that the second, third, fourth and fifth doped region of one such arrangement comprises a source/drain portion of a different one of four such arrangements adjacent to such one arrangement.

Claim 7

An electrically programmable, non-volatile memory cell array, in a semiconductor substrate, comprising a plurality of memory cell arrangements, each of said arrangements comprising: a first doped region in said substrate of a first conductivity type, having a central portion, and first, second, third and fourth source/drain portions extending outwardly from said central portion; second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first, second, third and fourth source/drain portions, respectively; a first and a second floating gate structure disposed on top of said channels formed between said first source/drain portion and said second doped region, and said second source/drain portion and said third doped region, respectively, and first and second control gate structures disposed on top of said first and said second floating gate structures, respectively, forming first and second storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and a third and a fourth floating gate structure disposed on top of said channels formed between said third source/drain portion and said fourth doped region, and said fourth source/drain portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming third and fourth storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said third source/drain portion and said fourth source/drain portion, respectively; wherein said memory cell arrangements are arranged in an array and interconnected such that the second, third, fourth and fifth doped region of one such arrangement comprises a source/drain portion of a different one of four such arrangements adjacent to such one arrangement.

Claim 8

An electrically programmable, non-volatile memory cell arrangement, in a semiconductor substrate, for use in an array, comprising: a first doped region in said substrate of a first conductivity type, having a central portion, first and second drain portions extending outwardly from said central portion, and first and second source portions extending outwardly from said central portion; second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first and second drain portions and said first and second source portions, respectively; a first and a second floating gate structure disposed on top of said channels formed between said first drain portion and said second doped region, and said second drain portion and said third doped region, respectively, and first and second control gate structures disposed on top of said first and said second floating gate structures, respectively, forming first and second storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and a third and a fourth floating gate structure disposed on top of said channels formed between said first source portion and said fourth doped region, and said second source portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming third and fourth storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said first source portion and said second source portion, respectively.

Claim 9

An electrically programmable, non-volatile memory cell arrangement, in a semiconductor substrate, for use in an array, comprising: a first doped region in said substrate of a first conductivity type, having a central portion, first and second drain portions extending outwardly from said central portion, and first and second source portions extending outwardly from said central portion; second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first and second drain portions and said first and second source portions, respectively; a first and a second floating gate structure disposed on top of said channels formed between said first drain portion and said second doped region, and said second drain portion and said third doped region, respectively, and first and second control gate structures disposed on top of said first and said second floating gate structures, respectively, forming first and second storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and a third and a fourth floating gate structure disposed on top of said channels formed between said first source portion and said fourth doped region, and said second source portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming third and fourth storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said first source portion and said second source portion, respectively.