MOSFET cell array

Claim 2

An array of memory cell transistors fabricated in rows and columns on a semiconductor substrate, comprising: thick field oxide regions on said substrate separating each said memory cell transistors in each said row from said memory cell transistor in adjacent said columns; an active area of said substrate between said thick field oxide regions and positioned at or below the level of lower surface of said thick field oxide regions on said substrate, for providing a fabrication base for said memory cell transistor components, each said active area defined by a two-tiered sidewall, of said field oxide region; said two-tiered sidewall having a sloped upper sidewall and a vertical or nearly vertical lower sidewall; and said memory cell transistors fabricated in said active areas of said substrate, each said memory cell transistor components including a gate, a drain, and a source.

Claim 3

The array of claim 1, and further comprising a channel stop region under said field oxide regions and the surface of said active areas of said substrate.

Claim 4

The array of claim 1, and further comprising a thin oxide layer covering said active areas of said substrate.

Claim 5

The array of claim 3, and further comprising a channel under said thin oxide layer covering said active areas of said substrate.

Claim 6

The array of claim 1, wherein a said gate of said memory cell transistor is fabricated over a gate oxide layer grown on each said active area of said substrate.

Claim 7

The array of claim 1, wherein said upper sidewall is formed by means of a resist pattern with tapered edges and a controlled etch of a layer of field oxide to form said field oxide region.

Claim 8

The array of claim 1, wherein said upper sidewall is formed by a direct etch of a layer of field oxide to form said field oxide region followed by fabrication of a sidewall oxide.

Claim 9

A array having rows and columns of transistor cells formed on a semiconductor substrate, made by a process that uses direct moat etching, comprising: a thick field oxide region separating each said transistor cell in a row from a transistor in an adjacent column, said thick field oxide region made by growing a layer of thick field oxide on said substrate and etching through said layer of thick field oxide to said substrate to form active areas on said substrate, said active areas at or below the level of the lower surface of said layer of thick field oxide, wherein each said active area is defined by sloped sidewalls of said thick field oxide regions, growing a thin oxide layer over said active area, and then etching a channel having vertical or nearly vertical walls through said thin oxide layer over said active area; and said transistor cells fabricated in said active areas, each said transistor cell having at least a gate, a drain, and a source.

Claim 10

A array having rows and columns of transistor cells formed on a semiconductor substrate, made by a process that uses direct moat etching, comprising: a thick field oxide region separating each said transistor cell in a row from a transistor in an adjacent column, said thick field oxide region made by growing a layer of thick field oxide on said substrate and etching through said layer of thick field oxide to said substrate to form active areas on said substrate, said active areas at or below the level of the lower surface of said layer of thick field oxide, wherein each said active area is defined by sloped sidewalls of said thick field oxide regions, growing a thin oxide layer over said active area, and then etching a channel having vertical or nearly vertical walls through said thin oxide layer over said active area; and said transistor cells fabricated in said active areas, each said transistor cell having at least a gate, a drain, and a source.

Claim 11

The memory array of claim 8, wherein said sloped sidewalls are made by patterning and etching a resist layer to define said active areas, such that the resist layer pattern has tapered edges, and then etching said layer of thick field oxide to replicate said tapered edges.

Claim 12

The memory array of claim 8, wherein said sloped sidewalls are made by patterning a resist layer to define said active areas, then etching said resist layer and said layer of thick field oxide to form said active areas with vertical or nearly vertical sidewalls of said thick field oxide regions, then forming oxide sidewalls along said vertical or nearly vertical sidewalls of said thick field oxide regions.

Claim 13

The memory array of claim 8, and further comprising a channel stop region under said field oxide regions and said active areas.

Claim 14

The memory cell array of claim 8, wherein said transistor cells are configured as memory cells for a flash-type electrically programmable and erasable memory cell array.

Claim 17

The method of claim 13, wherein said step of fabricating said active areas comprises patterning and etching a resist layer on said thick oxide layer to define said active areas, such that the resist layer pattern has tapered edges, and then etching said thick oxide layer to replicate said tapered edges.

Claim 18

The method of claim 13, wherein said step of fabricating said active areas comprises patterning a resist layer on said thick oxide layer to define said active areas, then etching said resist layer and said thick oxide layer to form said active areas with vertical or nearly vertical sidewalls of said field isolation regions, then forming oxide sidewalls along said vertical or nearly vertical sidewalls of said field isolation regions.

Claim 19

The method of claim 13, and further comprising the step of implanting boron to form a channel stop region under said field oxide regions and said active regions.

Claim 20

The method of claim 16, wherein said implanting step is performed after said step of fabricating said active areas and before said step of depositing said thin oxide layer.

Claim 21

The method of claim 16, wherein said implanting step is performed after said step of depositing said thin oxide layer.

Claim 22

The method of claim 13, and further comprising the step of growing a gate oxide layer over said channel.

Claim 23

The method of claim 13, wherein said step of etching said thin oxide layer completely removes said thin oxide layer.