US5023690A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Merged bipolar and complementary metal oxide semiconductor transistor device
Assignee: Texas Instruments Inc
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Filing: 1990-02-27
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Granted: 1991-06-11
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Expires: 2010-02-27
Abstract
Abstract A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.
Inventors
- 👤 Douglas P. Verret
- 👤 Michael C. Smayling
- 👤 Abnash C. Sachdeva
- 👤 Stephen A. Keller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:50
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53878; H02M7/4815; Y; Y02; Y02B; Y02B70/00; Y02B70/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
195 words
An integrated circuit comprising: (a) a layer of semiconductor material with a surface; (b) a first field effect transistor with channel region in a first N type region in said layer at said surface, said first N type region isolated by a first buried N+ region in said layer away from said surface plus insulator regions extending from the depth of and in contact with said first buried N+ layer to said surface; (c) a second field effect transistor with channel region in a first P type region in said layer at said surface, said first P type region isolated by a first buried P+ type region in said layer away from said surface plus insulator regions extending from the depth of and in contact with said first buried P+ layer to said surface; (d) a bipolar transistor with collector in a second N type region at said surface, said second N type region isolated by a second buried N+ region in said layer away from said surface plus insulator regions extending from the depth of and in contact with said second buried N+ layer to said surface; and (e) conductive interconnections among said transistors.
Claim 2
Dependent Claim
195 words
An integrated circuit comprising: (a) a layer of semiconductor material with a surface; (b) a first field effect transistor with channel region in a first N type region in said layer at said surface, said first N type region isolated by a first buried N+ region in said layer away from said surface plus insulator regions extending from the depth of and in contact with said first buried N+ layer to said surface; (c) a second field effect transistor with channel region in a first P type region in said layer at said surface, said first P type region isolated by a first buried P+ type region in said layer away from said surface plus insulator regions extending from the depth of and in contact with said first buried P+ layer to said surface; (d) a bipolar transistor with collector in a second N type region at said surface, said second N type region isolated by a second buried N+ region in said layer away from said surface plus insulator regions extending from the depth of and in contact with said second buried N+ layer to said surface; and (e) conductive interconnections among said transistors.
Claim 3
Dependent Claim
18 words
The integrated circuit of claim 1, wherein: (a) said insulator regions about corresponding ones of said buried regions.
Claim 4
Dependent Claim
15 words
The integrated circuit of claim 1, wherein: (a) said field effect transistors are silicon MOSFETs.
Claim 5
Dependent Claim
23 words
The integrated circuit of claim 1, wherein: (a) said layer is a P type substrate with an N type epilayer at said surface.
Claim 6
Dependent Claim
23 words
The integrated circuit of claim 1, further comprising: (a) a third N+ region extending from said second buried N+ region to said surface.
Claim 7
Dependent Claim
16 words
The integrated circuit of claim 1 wherein (a) said insulation regions are planarized at said surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-10 | 1994-12-10 | 1995-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-10 | 1998-12-10 | 1999-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-10 | 2002-12-10 | 2003-06-11 | $7700.00 | Window Closed / Lapsed |