Method for manufacturing semiconductor Bi-CMOS device

Claim 1

A method for manufacturing a semiconductor device, comprising the steps of: selectively forming, in a surface layer of a semiconductor substrate of a first conductivity type, a plurality of high concentration buried layers having a second conductivity type, and growing an epitaxial semiconductor layer of the first conductivity type on an entire surface of said substrate; forming well regions of the second conductivity type which extend from a surface of said epitaxial semiconductor layer to said high concentration buried layers; selectively forming a field insulating film on the surface of said epitaxial semiconductor layer so as to form first conductivity type element regions and second conductivity type element regions surrounded by said field insulating film; forming a thin insulating film on surfaces of said element regions; selectively doping one of said second conductivity type element regions with a first conductivity type impurity so as to form a first conductivity type active base region of a bipolar transistor; forming gate electrodes of MOS transistors interposed with said insulating film on said first conductivity type element regions and remaining ones of said second conductivity type element regions in which said active base region is not formed, said gate electrodes comprising polysilicon layers which are doped with an impurity to have a low resistance; forming a second conductivity type emitter region in said first conductivity type active base region; selectively doping a second conductivity type impurity so as to simultaneously form a second conductivity type collector contact region of said bipolar transistor, and second conductivity type source and drain regions of said MOS transistors in said first conductivity type element region, said second conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors; and selectively doping a first conductivity type impurity so as to form an external base region of the first conductivity type in said first conductivity type base region and first conductivity type source and drain regions of said MOS transistors in said remaining ones of said second conductivity type element regions, said first conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors.

Claim 2

A method for manufacturing a semiconductor device, comprising the steps of: selectively forming, in a surface layer of a semiconductor substrate of a first conductivity type, a plurality of high concentration buried layers having a second conductivity type, and growing an epitaxial semiconductor layer of the first conductivity type on an entire surface of said substrate; forming well regions of the second conductivity type which extend from a surface of said epitaxial semiconductor layer to said high concentration buried layers; selectively forming a field insulating film on the surface of said epitaxial semiconductor layer so as to form first conductivity type element regions and second conductivity type element regions surrounded by said field insulating film; forming a thin insulating film on surfaces of said element regions; selectively doping one of said second conductivity type element regions with a first conductivity type impurity so as to form a first conductivity type active base region of a bipolar transistor; forming gate electrodes of MOS transistors interposed with said insulating film on said first conductivity type element regions and remaining ones of said second conductivity type element regions in which said active base region is not formed, said gate electrodes comprising polysilicon layers which are doped with an impurity to have a low resistance; forming a second conductivity type emitter region in said first conductivity type active base region; selectively doping a second conductivity type impurity so as to simultaneously form a second conductivity type collector contact region of said bipolar transistor, and second conductivity type source and drain regions of said MOS transistors in said first conductivity type element region, said second conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors; and selectively doping a first conductivity type impurity so as to form an external base region of the first conductivity type in said first conductivity type base region and first conductivity type source and drain regions of said MOS transistors in said remaining ones of said second conductivity type element regions, said first conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors.