US4486942A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor integrated circuit BI-MOS device
Assignee: Mitsubishi Electric Corp
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Filing: 1983-03-24
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Granted: 1984-12-11
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Expires: 2003-03-24
Abstract
Abstract A method of manufacturing a semiconductor integrated circuit of the BI-MOS type on a common semiconductor substrate comprising forming an oxide film by thermal oxidation to isolate the elements and a base layer of one conductivity type by a surrounding dielectric followed by removing the oxide film from emitter and collector electrode extending regions. A silicon film of a second conductivity type is formed by patterning and used to form an emitter layer and a collector extending layer by differing impurities from the silicon film. Patterning is then employed to form gate, emitter and collector electrodes. Finally, the mask for the silicon film is used to form a base electrode extending layer, a source layer and a drain layer of the first conductivity type and of high impurity density.
Inventors
- 👤 Tadashi Hirao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:29
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10D; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
196 words
A method of manufacturing a BI-MOS semiconductor integrated device comprising: masking an epitaxial layer of a silicon substrate; selectively oxidizing said epitaxial layer to form a first oxide film whereby element forming regions are defined and electrically isolated from one another in a pattern as defined by said masking; diffusing an impurity of a first dopant type into one of said element forming regions, forming a base of said first dopant type; forming a second oxide film onto said epitaxial layer; removing said second oxide film at predetermined points corresponding with points of emitter and collector electrode contact with outside electrical leads; forming a silicon film of a second dopant type onto said epitaxial layer; masking and etching said silicon film, whereby emitter, collector and gate electrodes are formed of said second dopant type; diffusing impurities of said first dopant type into unmasked portions of said epitaxial layer, whereby base contact source and drain layers are formed which are of said first dopant type; annealing said epitaxial layer, whereby said emitter and collector electrodes diffuse into said element forming regions beneath them; and providing insulation and electrical contact means to electrically address said element forming regions.
Claim 2
Independent Claim
196 words
A method of manufacturing a BI-MOS semiconductor integrated device comprising: masking an epitaxial layer of a silicon substrate; selectively oxidizing said epitaxial layer to form a first oxide film whereby element forming regions are defined and electrically isolated from one another in a pattern as defined by said masking; diffusing an impurity of a first dopant type into one of said element forming regions, forming a base of said first dopant type; forming a second oxide film onto said epitaxial layer; removing said second oxide film at predetermined points corresponding with points of emitter and collector electrode contact with outside electrical leads; forming a silicon film of a second dopant type onto said epitaxial layer; masking and etching said silicon film, whereby emitter, collector and gate electrodes are formed of said second dopant type; diffusing impurities of said first dopant type into unmasked portions of said epitaxial layer, whereby base contact source and drain layers are formed which are of said first dopant type; annealing said epitaxial layer, whereby said emitter and collector electrodes diffuse into said element forming regions beneath them; and providing insulation and electrical contact means to electrically address said element forming regions.
Claim 3
Dependent Claim
37 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said first oxide films are disposed within said epitaxial layer such that a base forming region is electrically isolated from a collector forming region.
Claim 4
Dependent Claim
28 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said removing of said second oxide film is done by photomechanical processes or etching techniques.
Claim 5
Dependent Claim
25 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said silicon film comprises poly-crystalline silicon, epitaxial growth silicon or porous silicon.
Claim 6
Dependent Claim
17 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said insulation comprises phospho-silicate-glass.
Claim 7
Dependent Claim
30 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said first dopant type is one type, and said second dopant type is the opposite type, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |