US4445268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor integrated circuit BI-MOS device
Assignee: Mitsubishi Electric Corp
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Filing: 1982-02-12
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Granted: 1984-05-01
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Expires: 2002-02-12
Abstract
Abstract A method of manufacturing a semiconductor integrated circuit of the BI-MOS type on a common semiconductor substrate comprising forming an oxide film by thermal oxidation to isolate the elements and a base layer of one conductivity type by a surrounding dielectric followed by removing the oxide film from emitter and collector electrode extending regions. A silicon film of a second conductivity type is formed by patterning and used to form an emitter layer and a collector extending layer by differing purities from the silicon film. Patterning is then employed to form gate, emitter and collector electrodes. Finally, the mask for the silicon film is used to form a base electrode extending layer, a source layer and a drain layer of the first conductivity type and of high impurity density.
Inventors
- 👤 Tadashi Hirao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:12
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10D; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
193 words
A method of manufacturing a BI-MOS semiconductor integrated device, comprising: masking an epitaxial layer of a silicon substrate; selectively oxidizing said epitaxial layer to form a first oxide film whereby element formation regions are defined and electrically isolated from one another in a pattern as defined by said masking; forming a second oxide film on said epitaxial layer; masking said second oxide film; diffusing impurity ions through said second oxide film, whereby a base layer, a source layer and a drain layer are formed of a first dopant type; removing said second oxide film at predetermined points, whereby said predetermined points correspond with points where emitter and collector diffusion is to be completed; forming a silicon film on said epitaxial layer of a second dopant type; diffusing said silicon film into said element formation regions, such that both an emitter layer and a collector extending layer are formed of said second dopant type; removing said silicon film at predetermined points, whereby the remaining film forms a gate electrode, a collector electrode, and an emitter electrode, of said second dopant type; and providing insulation and electrical contact means to electrically address the transistor elements.
Claim 2
Independent Claim
193 words
A method of manufacturing a BI-MOS semiconductor integrated device, comprising: masking an epitaxial layer of a silicon substrate; selectively oxidizing said epitaxial layer to form a first oxide film whereby element formation regions are defined and electrically isolated from one another in a pattern as defined by said masking; forming a second oxide film on said epitaxial layer; masking said second oxide film; diffusing impurity ions through said second oxide film, whereby a base layer, a source layer and a drain layer are formed of a first dopant type; removing said second oxide film at predetermined points, whereby said predetermined points correspond with points where emitter and collector diffusion is to be completed; forming a silicon film on said epitaxial layer of a second dopant type; diffusing said silicon film into said element formation regions, such that both an emitter layer and a collector extending layer are formed of said second dopant type; removing said silicon film at predetermined points, whereby the remaining film forms a gate electrode, a collector electrode, and an emitter electrode, of said second dopant type; and providing insulation and electrical contact means to electrically address the transistor elements.
Claim 3
Dependent Claim
25 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said silicon film comprises poly-crystalline silicon, epitaxial growth silicon or porous silicon.
Claim 4
Dependent Claim
18 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said insulation comprises phosphorous glass.
Claim 5
Dependent Claim
30 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein said first dopant type is one type, and said second dopant type is the opposite type, respectively.
Claim 6
Dependent Claim
35 words
The method of manufacturing a BI-MOS semiconductor integrated device of claim 1, wherein both said removal of said second oxide film and said removal of said silicon film are completed by photomechanical processes or etching.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-01 | 1987-10-31 | 1988-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-01 | 1991-10-31 | 1992-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-01 | 1995-10-31 | 1996-05-01 | $7700.00 | Window Closed / Lapsed |