Method of manufacturing an insulated gate field effect device

Claim 1

A method of manufacturing an insulated gate field effect device in which an electrically insulating layer is formed on the surface of a semiconductor region of a first conductivity type at least in the area in which a gate electrode is to be formed, including depositing a polysilicon layer doped with a second conductivity type dopont on said insulating layer; providing a patterned masking layer on said polysilicon layer leaving a mask over the area in which the gate electrode is to be formed; diffusing said dopant from said polysilicon layer through said insulating layer into said semiconductor region on both sides of said mask thereby forming source and drain regions of a second conductivity type with lightly doped extensions, said diffusion being produced by heat treating said polysilicon in an oxidizing atmosphere whereby said polysilicon layer is oxidized; said oxidation being prevented where said mask is on said polysilicon layer except for portions which are laterally oxidized under the edges of said mask; said diffusion being prevented where said oxidation has been prevented, said unoxidized area forming said gate electrode; etching said oxidized layer to prepare said source and drain regions for an ion implantation step; and ion implanting a dopant into said source and drain regions to produce highly doped regions of said second conductivity type.

Claim 2

A method of manufacturing an insulated gate field effect device in which an electrically insulating layer is formed on the surface of a semiconductor region of a first conductivity type at least in the area in which a gate electrode is to be formed, including depositing a polysilicon layer doped with a second conductivity type dopont on said insulating layer; providing a patterned masking layer on said polysilicon layer leaving a mask over the area in which the gate electrode is to be formed; diffusing said dopant from said polysilicon layer through said insulating layer into said semiconductor region on both sides of said mask thereby forming source and drain regions of a second conductivity type with lightly doped extensions, said diffusion being produced by heat treating said polysilicon in an oxidizing atmosphere whereby said polysilicon layer is oxidized; said oxidation being prevented where said mask is on said polysilicon layer except for portions which are laterally oxidized under the edges of said mask; said diffusion being prevented where said oxidation has been prevented, said unoxidized area forming said gate electrode; etching said oxidized layer to prepare said source and drain regions for an ion implantation step; and ion implanting a dopant into said source and drain regions to produce highly doped regions of said second conductivity type.

Claim 8

A method according to claims 5 or 6, wherein the first conductivity type is a p-type semiconductor and said doped polysilicon is doped with an n-type dopant.

Claim 11

A method according to claims 5 or 6, wherein said first conductivity type is an n-type semiconductor and said doped polysilicon is doped with a p-type dopant.