Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines

Claim 1

In a process for providing self-aligned gate, source and drain contacts to corresponding regions of a FET device structure formed on an exposed surface area of a substrate having first defined field oxide regions, said FET device having a gate structure including a dielectric layer on the exposed sufrace area of the substrate covered by a polysilicon gate electrode, the improvement comprising: applying a layer of doped polysilicon having doping ions therein over the field oxide regions, the exposed surface area of the substrate, and the gate polysilicon electrode, applying a layer of silicon nitride over the doped polysilicon layer, delineating, using a single mask, silicon nitride outlined contact areas over the gates, sources, and drains of the FETs selectively removing portions of the silicon nitride layer to expose the polysilicon layer while retaining said silicon nitride outlined contact areas overlying the doped polysilicon layer portions which are juxtaposed on the source, drain and gate regions of the FET device to protect the said juxtaposed polysilicon layer portions, subjecting the structure to a thermal oxidation process to convert the exposed polysilicon layer to silicon dioxide and thereby produce cross-over silicon dioxide regions separating the gate structure of the FET device from the polysilicon layer portions juxtaposed on the source and drain regions of the FET device, and subjecting the structure to a selective material removal process which removes nitride material without materially affecting non-nitride material, to remove the silicon nitride outlined contact areas and expose the underlying surface of the protected polysilicon portions, said exposed polysilicon surfaces affording self-aligned electrical contact areas for each of the source, drain and gate regions of the FET device.