US4332076A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device
Assignee: US Philips Corp
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Filing: 1980-08-15
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Granted: 1982-06-01
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Expires: 2000-08-15
Abstract
Abstract A method of manufacturing a semiconductor device having at least one insulated gate field effect transistor in which a silicon body is provided with a silicon dioxide gate insulation layer and in which a boron-doped polysilicon electrode layer is formed on said layer, characterized in that the electrode layer is deposited by means of a low-pressure process, that the boron doping of the electrode layer is obtained by ion implantation, and that the silicon body is then subjected to a thermal treatment in an atmosphere containing hydrogen in which boron is diffused from the electrode layer through the gate insulation layer into a channel region underlying the electrode layer.
Inventors
- 👤 Jose Solo de Zaldivar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:35
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10P30/202; H10P30/204; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/1412; H10P32/17; H10P32/171; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/923
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
149 words
A method of manufacturing a boron-doped polysilicon gate semiconductor device having a silicon body and at least one insulated gate field effect transistor having a source region, of drain region and a channel region in the body, which comprises: forming a silicon dioxide gate insulation layer on said silicon body; depositing a polysilicon gate electrode layer on said silicon dioxide gate insulation layer and over said channel region in a low-pressure process; forming a boron source of substantially uniform thickness and reproducible boron concentration in the polysilicon gate electrode layer by boron doping the electrode layer by ion implantation; and then accurately controlling the threshold voltage of the device by subjecting the device to a thermal treatment in an atmosphere containing hydrogen to indiffuse the boron from the electrode layer, through the gate insulation layer and into the channel region of the field effect transistor underlying the electrode layer.
Claim 2
Independent Claim
149 words
A method of manufacturing a boron-doped polysilicon gate semiconductor device having a silicon body and at least one insulated gate field effect transistor having a source region, of drain region and a channel region in the body, which comprises: forming a silicon dioxide gate insulation layer on said silicon body; depositing a polysilicon gate electrode layer on said silicon dioxide gate insulation layer and over said channel region in a low-pressure process; forming a boron source of substantially uniform thickness and reproducible boron concentration in the polysilicon gate electrode layer by boron doping the electrode layer by ion implantation; and then accurately controlling the threshold voltage of the device by subjecting the device to a thermal treatment in an atmosphere containing hydrogen to indiffuse the boron from the electrode layer, through the gate insulation layer and into the channel region of the field effect transistor underlying the electrode layer.
Claim 3
Dependent Claim
21 words
A method as claimed in claim 1, characterized in that a p-channel field effect transistor of the enhancement type is manufactured.
Claim 4
Dependent Claim
37 words
A method as claimed in claim 2, characterized in that the boron doping of the electrode layer is carried out simultaneously with a boron implantation to obtain said source and drain zones of the field effect transistor.
Claim 5
Dependent Claim
42 words
A method as claimed in claim 3, further comprising a step to indiffuse boron ions implanted in the source and drain zones, said thermal treatment in an atmosphere containing hydrogen being at least partly concurrent with said step to indiffuse boron ions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-31 | 1985-11-30 | 1986-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-31 | 1989-11-30 | 1990-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-31 | 1993-11-30 | 1994-06-01 | $7700.00 | Window Closed / Lapsed |