Method of manufacturing an insulated gate field effect device and device manufactured by the method

Claim 1

A method of manufacturing an insulated gate field effect device, in which on a surface of a semiconductor region of a first conductivity type at least at the area of the gate electrode to be formed there is provided an electrically insulating layer and thereon a first silicon layer, whereupon a gate electrode is formed from the first silicon layer by etching and source and drain zone extensions of the second, opposite conductivity type are provided on either side of this electrode by implantation of ions at such an energy that at the area of the gate electrode the ions do not penetrate into the semiconductor region, and that highly doped contact portions of the source and drain zones are formed at a distance from the gate electrode determined in a self-aligning manner, characterized in that on the first silicon layer there is provided at least a first oxidation-preventing layer and thereon a second silicon layer, in that then a part of the second silicon layer is removed, the edges of the remaining part of this layer substantially coinciding with the edges of the gate electrode to be formed, in that subsequently at least the edge portions of the second silicon layer are thermally oxidized in a first oxidation step, whereupon the uncovered parts of the first oxidation-preventing layer are etched away selectively, in that then the oxidized edge portions are etched away and the exposed silicon surface is thermally oxidized in a second oxidation step, in that subsequently the exposed parts of the first oxidation-preventing layer are etched away and then the parts of the first silicon layer thus exposed are etched away at least down to the insulating layer, in that through the openings in the first silicon layer thus obtained the source and drain zone extensions are implanted, whereupon the exposed oxide layers are etched away and in that during a third oxidation step the silicon thus exposed is provided with a thermal oxide layer.

Claim 2

A method of manufacturing an insulated gate field effect device, in which on a surface of a semiconductor region of a first conductivity type at least at the area of the gate electrode to be formed there is provided an electrically insulating layer and thereon a first silicon layer, whereupon a gate electrode is formed from the first silicon layer by etching and source and drain zone extensions of the second, opposite conductivity type are provided on either side of this electrode by implantation of ions at such an energy that at the area of the gate electrode the ions do not penetrate into the semiconductor region, and that highly doped contact portions of the source and drain zones are formed at a distance from the gate electrode determined in a self-aligning manner, characterized in that on the first silicon layer there is provided at least a first oxidation-preventing layer and thereon a second silicon layer, in that then a part of the second silicon layer is removed, the edges of the remaining part of this layer substantially coinciding with the edges of the gate electrode to be formed, in that subsequently at least the edge portions of the second silicon layer are thermally oxidized in a first oxidation step, whereupon the uncovered parts of the first oxidation-preventing layer are etched away selectively, in that then the oxidized edge portions are etched away and the exposed silicon surface is thermally oxidized in a second oxidation step, in that subsequently the exposed parts of the first oxidation-preventing layer are etched away and then the parts of the first silicon layer thus exposed are etched away at least down to the insulating layer, in that through the openings in the first silicon layer thus obtained the source and drain zone extensions are implanted, whereupon the exposed oxide layers are etched away and in that during a third oxidation step the silicon thus exposed is provided with a thermal oxide layer.

Claim 7

A method as claimed in anyone of the preceding claims, characterized in that the insulating layer is provided substantially only at the area of the gate electrode to be formed.

Claim 8

A method as claimed in anyone of the preceding claims, characterized in that the second silicon layer is removed at the area of the gate electrode to be formed.

Claim 10

A method as claimed in anyone of Claims 1 to 6, characterized in that on removing a part of the second silicon layer, the part at the area of the gate electrode to be formed remains.

Claim 12

A method as claimed in anyone of the preceding claims, characterized in that at least one oxidation-preventing layer comprises silicon nitride.

Claim 13

A method as claimed in anyone of the preceding Claims, characterized in that the extensions of the source and drain zones have different doping concentrations.

Claim 14

A method as claimed in anyone of the preceding Claims, characterized in that the insulating layer consists of silicon oxide.

Claim 15

A method as claimed in anyone of the preceding claims, characterized in that the semiconductor region of the first conductivity type consists of silicon.