Non-volatile eprom with increased efficiency

Claim 2

A reprogrammable nonvolatile EPROM cell comprising: a semiconductor substrate containing a source region and a drain region; a floating gate positioned such that a substantial portion of the floating gate is above but insulated from the drain region and the remainder of the floating gate extends over but is insulated from a portion of the channel region between the drain and the source; a control gate insulated from but extending over both the floating gate and the remainder of the channel region between the source and the drain such that that portion of the control gate not over the floating gate is positioned more closely to that portion of the channel region between the source and the drain not covered by the floating gate than is the portion of the control gate overlying the floating gate.

Claim 3

Structure as in claim 1 wherein a capacitance Cd exists between the drain and the floating gate and a capacitance Cc exists between the floating gate and the control gate and the ratio of Cd to Cc is equal to or greater than approximately 0.1.

Claim 4

Structure as in claim 1 wherein the ratio of the capacitance Cd between the drain region and the floating gate to the capacitance Cc between the floating gate and the control gate is equal to or greater than approximately 0.3.

Claim 5

Structure as in claim 1 wherein said floating gate comprises a first layer of polycrystalline silicon insulated from the underlying substrate by a first dielectric layer and said control gate comprises a second layer of conductive material insulated from said first layer of polycrystalline silicon by a second dielectric.

Claim 6

Structure as in claim 4 wherein said second conductive layer comprises a second layer of polycrystalline silicon.

Claim 7

Structure as in claim 1 wherein the channel region between said source and drain regions comprises a middle portion possessing a first selected dopant concentration selected to minimize the threshold voltage required to turn on said cell and wherein the edges of said channel region adjacent to the field of the device are more highly doped in order to increase the efficiency of hot electron injection from the channel into the floating gate during the programming of the cell.

Claim 8

A nonvolatile reprogrammable EPROM array containing M×N memory cells, where M is a first selected integer equal to the number of columns of memory cells in the array, and N is a second selected integer equal to the number of rows in the array, comprising: a semiconductor substrate of one conductivity type in which are formed a first plurality of M+1 strips of source-drain regions of opposite conductivity type; a second plurality of M×N regions of first conductive material comprising M sets of N regions each of first conductive material, each set of N regions of first conductive material being insulated from but formed over a substantial portion of a corresponding one of said source-drain regions, each of said N regions of first conductive material in a set being formed over a portion of a corresponding one of said source-drain regions and over a portion of a channel region in the substrate adjacent to the source-drain region, whereby each of said regions of first conductive material in a given set of N regions of first conductive material is electrically insulated from the underlying source-drain region and the underlying channel region; insulation formed over said second plurality of M×N regions of first conductive material; a third plurality of N strips of second conductive material formed in a direction perpendicular to the M+1 strips of source-drain regions, said strips of second conductive material overlying and being insulated from said second plurality of M×N regions of first conductive material, M regions in a row from said second plurality of M×N regions of first conductive material underlying but insulated from one of said N strips of second conductive material; insulation over said third plurality of N strips of second conductive material; a fourth plurality of M+1 conductive strips formed on said insulation overlying and parallel to, on a one-to-one basis said first plurality of M+1 strips of source-drain regions; and means for electrically connecting each of said fourth plurality of M+1 conductive strips to a corresponding one of said first plurality of M+1 strips of source-drain regions, said means for electrically connecting comprising selected electrically conductive paths formed between each of said fourth plurality of conductive strips and the underlying one of said source-drain regions, each of said conductive paths being separated from the adjacent conductive paths connecting said conductive strip to said underlying source-drain region by at least k of said third plurality of N strips of second conductive material where k is a selected integer.

Claim 9

A nonvolatile reprogrammable EPROM array containing M×N memory cells, where M is a first selected integer equal to the number of columns of memory cells in the array, and N is a second selected integer equal to the number of rows in the array, comprising: a semiconductor substrate of one conductivity type in which are formed a first plurality of M+1 strips of source-drain regions of opposite conductivity type; a second plurality of M×N regions of first conductive material comprising M sets of N regions each of first conductive material, each set of N regions of first conductive material being insulated from but formed over a substantial portion of a corresponding one of said source-drain regions, each of said N regions of first conductive material in a set being formed over a portion of a corresponding one of said source-drain regions and over a portion of a channel region in the substrate adjacent to the source-drain region, whereby each of said regions of first conductive material in a given set of N regions of first conductive material is electrically insulated from the underlying source-drain region and the underlying channel region; insulation formed over said second plurality of M×N regions of first conductive material; a third plurality of N strips of second conductive material formed in a direction perpendicular to the M+1 strips of source-drain regions, said strips of second conductive material overlying and being insulated from said second plurality of M×N regions of first conductive material, M regions in a row from said second plurality of M×N regions of first conductive material underlying but insulated from one of said N strips of second conductive material; insulation over said third plurality of N strips of second conductive material; a fourth plurality of M+1 conductive strips formed on said insulation overlying and parallel to, on a one-to-one basis said first plurality of M+1 strips of source-drain regions; and means for electrically connecting each of said fourth plurality of M+1 conductive strips to a corresponding one of said first plurality of M+1 strips of source-drain regions, said means for electrically connecting comprising selected electrically conductive paths formed between each of said fourth plurality of conductive strips and the underlying one of said source-drain regions, each of said conductive paths being separated from the adjacent conductive paths connecting said conductive strip to said underlying source-drain region by at least k of said third plurality of N strips of second conductive material where k is a selected integer.

Claim 10

Structure as in claim 7 wherein k is equal to or greater than eight.

Claim 11

Structure as in claim 8 wherein each of the cells in said array of memory cells comprises a portion of a first source-drain region overlain by a region of said first conductive material insulated from said first source-drain region, said region of said first conductive material overlying a substantial portion of said first source-drain region and a substantial portion of a channel region adjacent to said first source-drain region; insulation overlying said region of said first conductive material; a conductive gate insulated from said region of said first conductive material but overlying said region of said first conductive material, said conductive gate extending over a portion of said channel region not covered by said region of said first conductive material, said conductive gate extending closer to said channel region in the area where said channel region is not overlain by said region of said first conductive material; insulation overlying said conductive gate; and a second source-drain region at the opposite end of said channel region.

Claim 12

Structure as in claim 9 including means for applying a first potential to said first source-drain region; means for applying a second potential to said conductive gate and means for sensing the state of the channel region underlying said conductive gate and said region of said first conductive material during the application of said second potential to said conductive gate and said first potential to said source-drain region.

Claim 13

Structure as in claim 9 wherein a portion of the insulation underneath said region of said first conductive material is selectively thinner than the other portions of said insulation thereby to allow electrons to tunnel through said thinner portion of insulation from said region of said first conductive material to the underlying substrate.