US4247916A
Expired / Lapsed
US
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Memory device in which one type carrier stored during write controls the flow of the other type carrier during read
Assignee: Advanced Micro Devices Inc
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Filing: 1979-10-30
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Granted: 1981-01-27
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Expires: 1999-10-30
Abstract
Abstract A RAM device employs an array of dual gated transistor memory cells accessed by row and column decoding. A separate P type memory region is provided under the column gate which acquires holes as a function of the input data during the write cycle, for controlling the flow of an output electron current during the subsequent read cycle. The write holes flow from the substrate into the P memory region to record a "1" when both the row gate and the column gate are at a low positive potential. The write holes become trapped in the P memory region when the low write voltage on the row gate is replaced by a higher storage voltage. During the read cycle both gates are high, and electron current flows from source to drain along a continuous electron conductive path formed under both gates. The high row voltage causes electron conduction at the surface of the P substrate under the row gate by establishing an N type inversion layer. The high column voltage in combination with the positive charge of the write holes promotes the flow of read electrons under the column gate through a buried N channel adjacent to the P memory region. The read conductive path between the source and drain is formed by the row inversion layer plus the N channel. The stratified charge structure functions as an additional gate beneath the column gate which requires trapped write holes in order to allow electron flow when the row and column gates are activated during read.
Inventors
- 👤 Darrell M. Erb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
346 words
A random access memory capable of writing and storing data in and reading data out, formed by an array of semiconductor switches responsive to electrical control signals for redistributing carriers of one polarity type during writing as a function of data in, which redistributed carriers at least partially determine the data out current of the opposite polarity type carriers during reading, comprising: a semiconductor substrate means of the one polarity type formed by a bulk portion and a processed portion; a plurality of spaced source means and drain means of the opposite plurality type within the processed portion of the substrate means, and extending thereacross defining the array of semiconductor switches; read path means within the processed portion of the substrate means between the source means and the drain means of each semiconductor switch for conducting the data out current during read; memory storage means within the processed portion of the substrate means switch proximate the read path of each semiconductor switch, which receives a controlled quantity of carriers of the one polarity type from the bulk portion of the substrate means during writing as a function of the data in for determining the data out current between the source means and the drain means during read; isolation means at least a portion of which is dynamic for storing carriers of the one polarity type in the memory storage means. write path means within the processed portion of the substrate means, one for each semiconductor switch communicating between the memory storage means and the bulk portion of the substrate means for conducting the one polarity type carrier redistributed during writing; and control means proximate the path means within each semiconductor switch, responsive to the electrical control signals for establishing electrical fields which control the dynamic portion of the isolation means permitting control of the redistribution of the one polarity type carriers as a function of data in, and which promote data out current of the opposite polarity type carriers during read as a function of the one polarity type carriers stored in the memory storage means.
Claim 2
Dependent Claim
346 words
A random access memory capable of writing and storing data in and reading data out, formed by an array of semiconductor switches responsive to electrical control signals for redistributing carriers of one polarity type during writing as a function of data in, which redistributed carriers at least partially determine the data out current of the opposite polarity type carriers during reading, comprising: a semiconductor substrate means of the one polarity type formed by a bulk portion and a processed portion; a plurality of spaced source means and drain means of the opposite plurality type within the processed portion of the substrate means, and extending thereacross defining the array of semiconductor switches; read path means within the processed portion of the substrate means between the source means and the drain means of each semiconductor switch for conducting the data out current during read; memory storage means within the processed portion of the substrate means switch proximate the read path of each semiconductor switch, which receives a controlled quantity of carriers of the one polarity type from the bulk portion of the substrate means during writing as a function of the data in for determining the data out current between the source means and the drain means during read; isolation means at least a portion of which is dynamic for storing carriers of the one polarity type in the memory storage means. write path means within the processed portion of the substrate means, one for each semiconductor switch communicating between the memory storage means and the bulk portion of the substrate means for conducting the one polarity type carrier redistributed during writing; and control means proximate the path means within each semiconductor switch, responsive to the electrical control signals for establishing electrical fields which control the dynamic portion of the isolation means permitting control of the redistribution of the one polarity type carriers as a function of data in, and which promote data out current of the opposite polarity type carriers during read as a function of the one polarity type carriers stored in the memory storage means.
Claim 3
Dependent Claim
63 words
The random access memory of claim 1, wherein the control means include: write path gate means proximate the write path for providing the electric field which controls the conductivity of the write path memory gate means proximate the memory means for providing the electric field which controls the quantity of redistributed carriers received by the memory means when the write path is conductive.
Claim 4
Dependent Claim
25 words
The random access memory of claim 2, wherein each semiconductor switch has a plurality of memory regions with a memory gate proximate each memory region.
Claim 5
Dependent Claim
109 words
The random access memory of claim 3, wherein each semiconductor switch comprises: a first memory region of the one polarity type proximate the source means for that semiconductor switch, a second memory region of the one polarity type proximate the drain means for that semiconductor switch, a write gate between the gate of the first memory region and the gate of the second memory region; a first region of the opposite polarity type extending from the source means towards the write gate under the first memory region; and a second region of opposite polarity type extending from the drain means toward the write gate under the second memory region.
Claim 6
Dependent Claim
49 words
The random access memory of claim 2, wherein the array of semiconductor switches is arranged in a row by column matrix, and the control means within each semiconductor switch includes row accessing gate means and column accessing gate means for individually accessing each semiconductor switch for writing and reading.
Claim 7
Dependent Claim
89 words
The random access memory of claim 5, wherein: the write path gate means and one of the accessing gate means is formed by a single first electrode structure positioned between the source means and drain means within each switch proximate the write path means; and the memory gate means and the other one of the accessing gate means is formed by a single electrode structure positioned between the source means and the drain means within each switch proximate the memory means in series relationship with the first electrode structure.
Claim 8
Dependent Claim
168 words
The random access memory of claim 6, wherein: the first electrode structure receives a first storage control signal of the one polarity relative to the substrate means when the first electrode structure is not being accessed to write or to read, for establishing a depletion region in at least that portion of the write path means proximate the first electrode structure for preventing the conduction of the one polarity type carriers; the second electrode structure receives a second storage control signal of the one polarity type relative to the substrate means when the second electrode structure is not being accessed to write or to read, for inhibiting further transfer of the one polarity type carrier into the memory means; and at least one of the electrode structures receives a read control signal for permitting carriers of the opposite polarity type to flow along the read path means between the source means and the drain means subject to the intensity of the redistributed charge contained in the memory means.
Claim 9
Dependent Claim
125 words
The random access memory of claim 6, wherein; the write path means is a semiconductor material of the one polarity type; the first electrode structure receives a write control signal during writing in order to access the semiconductor switch for writing, and to render the write path means conductive permitting the one polarity type carriers to accumulate proximate thereto for entry into the memory means; and the second electrode structure receives a data in control signal during writing in order to access the semiconductor switch for writing and for controlling the quantity of redistributed carriers received by the memory means through the write path means from the bulk portion of the substrate means while the write control signal is applied to the first electrode structure.
Claim 10
Dependent Claim
85 words
The random access memory of claim 8, wherein the data in control signal has two voltage levels, one level of which permits a greater charge of redistributed carriers of the one polarity type to enter the memory means during writing and the other level of which permit a lesser charge of redistributed carriers of the one polarity type to enter the memory means during writing, for defining two data out current levels of the opposite polarity type carriers in the read path means during reading.
Claim 11
Dependent Claim
43 words
The random access memory of claim 8, wherein the data in control signal varies over a range of voltage levels for permitting a corresponding range of redistributed charge intensities with in the memory means for defining a range of data out current levels.
Claim 12
Dependent Claim
133 words
The random access memory of claim 8, wherein: the read path means extends between the source means and the drain means proximate the first and second electrode structures and the memory storage means, for conducting data out current of the opposite polarity type carriers in response to redistributed charge within the memory storage means when both electrode structures are accessed for reading, the portion of the read path means proximate the second electrode structure is of the opposite polarity type; and the memory storage means is between the second electrode structure and the opposite polarity type portion of the read path, and cooperates with a second read control signal applied to the second electrode to control the flow of data out current in the adjacent opposite polarity type portion of the read path.
Claim 13
Dependent Claim
21 words
The random access memory of claim 1, wherein the memory storage means is a semiconductor region of the one polarity type.
Claim 14
Dependent Claim
39 words
The random access memory of claim 11, wherein the memory storage means is a surface layer of the one polarity type along the interface between the second electrode structure and the opposite polarity type portion of the read path.
Claim 15
Dependent Claim
150 words
The random access memory of claim 11, wherein; the source means and the drain means are busses of the opposite polarity type diffused into the substrate means and extending on either side of each semiconductor switch; the opposite polarity type portion of the read path of each semiconductor switch is in electrical contact with the drain means, and is depleted of opposite polarity type carriers by the drain voltage during writing; and the portion of the read path proximate the first electrode is in electrical contact with the source means, and is of the one polarity type conductive to opposite type polarity carriers in response to a first read control signal applied to the first electrode which causes an opposite type polarity inversion region to extend from the source means along the one polarity type portion of the read path to the opposite type polarity portion of the read path.
Claim 16
Dependent Claim
102 words
The random access memory of claim 14, wherein: the first electrode structure is proximate the source means and is the row access gate, and the second electrode is proximate the drain means and is the column access gate; each semiconductor switch is write accessed by the write control signal applied to the first electrode structure in combination with the data in control signal applied to the second electrode structure; and each semiconductor switch is read accessed by a first read control signal applied to the first electrode structure in combination with a second read control signal applied to the second electrode structure.
Claim 17
Dependent Claim
21 words
The random access memory of claim 15, wherein the one polarity type is P and the opposite polarity type is N.
Claim 18
Dependent Claim
30 words
The random access memory of claim 11, wherein the isolation means surrounds the memory storage means during storage and reading for preventing the conduction of both polarity type carriers thereinto.
Claim 19
Dependent Claim
49 words
The random access memory of claim 17, wherein the dynamic portion of the isolation means is along the side of the memory storage means facing the source means, and is a depletion region formed in the adjacent write path by the control signals applied to the first electrode structure.
Claim 20
Dependent Claim
211 words
A semiconductor switch having a plurality of stored charge levels therein formed by one polarity carriers and a corresponding plurality of current levels therethrough formed by the opposite polarity carriers and responsive to control signals applied to the semiconductor switch, comprising: a base means for supporting the semiconductor switch; a first terminal means carried by the base means; a second terminal means carried by the base means in spaced relationship to the first terminal means; control means carried by the base means responsive to the control signals for controlling the charge and current levels; a current path between the first terminal means and the second terminal which becomes conductive for carriers of the opposite polarity in response to the control means; memory means proximate the current path and responsive to the control means for receiving one of the plurality of stored charge levels of the one polarity carriers to maintain one of the plurality of current levels of carriers of the opposite polarity in the current path when current flows therein; a reservoir of carriers of the one polarity carried by the base means; and a charge path between the memory means and the reservoir of carriers for conducting carriers of the one polarity therebetween in response to the control means.
Claim 21
Dependent Claim
211 words
A semiconductor switch having a plurality of stored charge levels therein formed by one polarity carriers and a corresponding plurality of current levels therethrough formed by the opposite polarity carriers and responsive to control signals applied to the semiconductor switch, comprising: a base means for supporting the semiconductor switch; a first terminal means carried by the base means; a second terminal means carried by the base means in spaced relationship to the first terminal means; control means carried by the base means responsive to the control signals for controlling the charge and current levels; a current path between the first terminal means and the second terminal which becomes conductive for carriers of the opposite polarity in response to the control means; memory means proximate the current path and responsive to the control means for receiving one of the plurality of stored charge levels of the one polarity carriers to maintain one of the plurality of current levels of carriers of the opposite polarity in the current path when current flows therein; a reservoir of carriers of the one polarity carried by the base means; and a charge path between the memory means and the reservoir of carriers for conducting carriers of the one polarity therebetween in response to the control means.
Claim 22
Dependent Claim
40 words
The semiconductor switch of claim 19, wherein the control means includes a charge path control means which controls the conduction of the one polarity type carriers along the charge path by establishing and disrupting the continuity of the charge path.
Claim 23
Dependent Claim
47 words
The semiconductor switch of claim 20, wherein the plurality of memory charge control signals form a continuous range of voltage levels which support a continuous range of memory charge electric field intensities defining a continuous range of stored charge levels and a continuous range of current levels.
Claim 24
Dependent Claim
53 words
The semiconductor switch of claim 20, wherein the charge path control means is responsive to charge path control signals for establishing the continuity of the charge path in order for the memory means to receive one of the plurality of stored charge levels, and for disrupting the continuity of the charge path thereafter.
Claim 25
Dependent Claim
28 words
The semiconductor switch of claim 22, wherein the charge path control signals include a continuity signal and a discontinuity signal for controlling the continuity of the charge path.
Claim 26
Dependent Claim
16 words
The semiconductor switch of claim 23, wherein the charge path control signals are direct current voltages.
Claim 27
Dependent Claim
31 words
The semiconductor switch of claim 24, wherein the charge path control signals are direct current voltages of the one polarity with respect to and the discontinuity voltage exceeds the continuity voltage.
Claim 28
Dependent Claim
32 words
The semiconductor switch of claim 22, wherein the control means includes a memory charge control means for controlling the flow of one polarity carriers from the charge path into the memory means.
Claim 29
Dependent Claim
30 words
The semiconductor switch of claim 26, wherein the memory charge control means is responsive to memory charge control signals for establishing the level of the charge stored in the memory.
Claim 30
Dependent Claim
26 words
The semiconductor switch of claim 27, wherein the memory charge control signals include a plurality of bias levels for defining the plurality of stored charge levels.
Claim 31
Dependent Claim
42 words
The semiconductor switch of claim 27, wherein the charge path control means is a gate means proximate the charge path which provides a charge path electric field in response to the charge control signals for controlling the continuity of the charge path.
Claim 32
Dependent Claim
40 words
The semiconductor switch of claim 29, wherein the storage path control gate means has an electrode member responsive to discrete voltage levels of the charge path control signals to provide discrete charge path electric field intensities in the charge path.
Claim 33
Dependent Claim
76 words
The semiconductor switch of claim 30, wherein the charge control signals have two discrete voltage levels: a continuity voltage level which supports conduction of the one polarity carriers; and a discontinuity voltage level which provides a charge path electric field sufficient to create a depletion condition of the one polarity type within at least a portion of the charge path thus preventing conduction of the one polarity carriers between the memory means and the reservoir means.
Claim 34
Dependent Claim
37 words
The semiconductor switch of claim 31, wherein the memory charge control means is a gate means proximate the memory means which provides a memory charge electric field within the memory means for determining the charge level thereof.
Claim 35
Dependent Claim
42 words
The semiconductor switch of claim 32, wherein the memory charge gate means includes an electrode responsive to a plurality of memory charge control signals for providing a plurality of memory charge electric field intensities which define the plurality of stored charge levels.
Claim 36
Dependent Claim
35 words
The semiconductor switch of claim 33, wherein the plurality of memory charge control signals have discrete voltage levels which support discrete memory charge electric field intensities defining discrete stored charge levels within the memory means.
Claim 37
Dependent Claim
30 words
The semiconductor switch of claim 34, wherein the memory charge control signals have two discrete levels which support two discrete memory charge electric fields defining two discrete stored charge levels.
Claim 38
Dependent Claim
67 words
The semiconductor switch of claim 35, wherein one of the discrete stored charge level is a high charge of the one polarity carriers which results in a correspondingly high current flow of the opposite polarity carriers, and the other of the discrete stored charge levels is a low charge of the one polarity carriers which results in a correspondingly low current flow of the opposite polarity carriers.
References Cited (Backward Citations)
US3728695A
Cited
US3971055A
Cited
US4000504A
Cited
US4090257A
Cited
US4122543A
Cited
US4112575A
Cited
US4126900A
Cited
US4158238A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-27 | 1984-07-28 | 1985-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-27 | 1988-07-28 | 1989-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-27 | 1992-07-28 | 1993-01-27 | $7700.00 | Window Closed / Lapsed |