Analog memory circuit utilizing a field effect transistor for signal storage

Claim 2

An analogue memory circuit comprising, a substrate of a first conductivity type, first and second electrodes connected to said substrate and spaced apart to form a current channel therebetween, a first region of opposite conductivity type formed in said substate between said first and second electrodes and forming a first PN junction, a second region of first conductivity type formed in said first and forming a second PN junction, means for applying a signal of a first polarity to said second region so as to forward bias said second PN junction and to reverse bias said first PN junction so that a charge proportional so said input signal is stored in said first region, means for applying a blanking signal to said memory circuit to neutralize said charge stored in said first region, and an output terminal connected to said memory circuit to remove a signal proportional to said stored input signal.

Claim 3

An analogue memory circuit according to claim 1 wherein said means for applying a blanking signal includes a third region of opposite conductivity type formed in said substrate adjacent to but separated from said first region and said blanking signal applied to said third region.

Claim 4

An analogue memory circuit according to claim 2 wherein said substrate, first and second electrodes and said first and second regions comprise a charge storage junction type field effect transistor.

Claim 5

An analogue memory circuit according to claim 1 wherein said means for applying a blanking signal includes a third electrode connected to said first region, a field effect transistor having a source, drain and a gate, the source drain current path of said field effect transistor connected to said third electrode and said blanking signal applied to said gate to bias said field effect on and to neutralize said charge stored in said first region.

Claim 6

An analogue memory circuit according to claim 4 wherein said drain is connected to said third electrode.

Claim 7

An analogue memory circuit according to claim 2 wherein said third region and said second region are electrically connected together and said input signal and said blanking signal are applied to said second and third regions.

Claim 8

An analogue memory circuit comprising, a substrate of a first conductivity type, first and second spaced regions of opposite conductivity type formed in said substrate, first and second electrodes spaced apart in said first region, a third region of first conductivity type formed between said first and second electrodes, fourth and fifth spaced regions of first conductivity type formed in said second region, a sixth region of opposite conductivity type formed in said fourth region, said third and sixth regions electrically connected together, an input signal terminal connected to said sixth region, a blanking signal terminal connected to said fifth region, and an output terminal connected to said second electrode.

Claim 9

An analogue memory circuit comprising, a substrate of a first conductivity type, first and second spaced regions of opposite conductivity type formed in said substrate, first and second electrodes spaced apart in said first region, a third region of first conductivity type formed between said first and second electrodes, fourth and fifth spaced regions of first conductivity type formed in said second region, a sixth region of opposite conductivity type formed in said fourth region, said third and sixth regions electrically connected together, an input signal terminal connected to said sixth region, a blanking signal terminal connected to said fifth region, and an output terminal connected to said second electrode.

Claim 10

An analogue memory circuit comprising, a substrate of a first conductivity type, an insulating layer formed on said substrate, first and second regions of opposite conductivity type formed in said substrate and spaced from each other, a first gate electrode formed on said insulating layer between said first and second regions, a third region of opposite conductivity type formed in said substrate, a fourth region of first conductivity type formed in said third region, fifth and sixth regions of opposite conductivity type formed in said substrate and spaced from each other, a second gate electrode formed on said insulating layer between said fifth and sixth regions, first, second, third, fourth, fifth and sixth electrodes respectively, connected to said first, second, third, fourth, fifth and sixth regions, said first gate electrode electrically connected to said fourth and fifth electrodes, an input signal connected to said third electrode, a blanking signal connected to said second gate electrode, an output terminal connected to said second electrode, said first and sixth electrodes connected together and to a reference point, an impedance, a voltage source, and said impedance connected between said reference point and said output terminal.

Claim 11

An analogue memory circuit comprising, a substrate of a first conductivity type, an insulating layer formed on said substrate, first and second regions of opposite conductivity type formed in said substrate and spaced from each other, a first gate electrode formed on said insulating layer between said first and second regions, a third region of opposite conductivity type formed in said substrate, a fourth region of first conductivity type formed in said third region, fifth and sixth regions of opposite conductivity type formed in said substrate and spaced from each other, a second gate electrode formed on said insulating layer between said fifth and sixth regions, first, second, third, fourth, fifth and sixth electrodes respectively, connected to said first, second, third, fourth, fifth and sixth regions, said first gate electrode electrically connected to said fourth and fifth electrodes, an input signal connected to said third electrode, a blanking signal connected to said second gate electrode, an output terminal connected to said second electrode, said first and sixth electrodes connected together and to a reference point, an impedance, a voltage source, and said impedance connected between said reference point and said output terminal.