US6778441B2 — Integrated circuit memory device and method

Claim 1

Independent Claim 201 words

A DEAPROM memory array, comprising: a number of DEAPROM memory cells, wherein each DEAPROM memory cell includes: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region in the number of pillars and separated therefrom by a gate oxide. a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the DEAPROM memory array; a number of control gate lines coupled to the control gates along a second selected direction in the DEAPROM memory array; a number of bitlines coupled to the second source/drain regions along a third selected direction in the DEAPROM memory array; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 2

Dependent Claim 201 words

A DEAPROM memory array, comprising: a number of DEAPROM memory cells, wherein each DEAPROM memory cell includes: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region in the number of pillars and separated therefrom by a gate oxide. a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the DEAPROM memory array; a number of control gate lines coupled to the control gates along a second selected direction in the DEAPROM memory array; a number of bitlines coupled to the second source/drain regions along a third selected direction in the DEAPROM memory array; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 3

Dependent Claim 75 words

The DEAPROM memory array of claim 1 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 4

Dependent Claim 48 words

The DEAPROM memory array of claim 1 , wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 5

Dependent Claim 48 words

The DEAPROM memory array of claim 1 , wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 6

Dependent Claim 42 words

The DEAPROM memory array of claim 1 , wherein the second selected direction and the third selected direction are parallel to one another and orthogonal to the first selected direction, and wherein the number of control gate lines serve as address lines.

Claim 7

Dependent Claim 42 words

The DEAPROM memory array of claim 1 , wherein the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction, and wherein the number of control gate lines serve as address lines.

Claim 8

Dependent Claim 40 words

The DEAPROM memory array of claim 1 , wherein the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction, and wherein the number of bitlines serve as address lines.

Claim 9

Dependent Claim 219 words

An array of DEAPROM memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates arc separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells ; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 10

Dependent Claim 219 words

An array of DEAPROM memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates arc separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells ; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 11

Dependent Claim 77 words

The array of DEAPROM memory cells of claim 8 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 12

Dependent Claim 50 words

The array of DEAPROM memory cells of claim 8 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 13

Dependent Claim 50 words

The array of DEAPROM memory cells of claim 8 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 14

Dependent Claim 68 words

The array of DEAPROM memory calls of claim 8 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 15

Dependent Claim 74 words

The array of DEAPROM memory cells of claim 8 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 16

Dependent Claim 37 words

The array of DEAPROM memory cells of claim 8 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

Claim 17

Dependent Claim 47 words

The array of DEAPROM memory cells of claim 8 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control gate lines.

Claim 18

Dependent Claim 75 words

The array of DEAPROM memory cells of claim 8 , wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 19

Dependent Claim 24 words

The array of DEAPROM memory cells of claim 16 , wherein the plurality of control gate lines are disposed vertically above the floating gates.

Claim 20

Dependent Claim 228 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of DEAPROM memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells, a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates fire separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 21

Dependent Claim 228 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of DEAPROM memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells, a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates fire separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 22

Dependent Claim 74 words

The electronic system of claim 18 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 23

Dependent Claim 46 words

The electronic system of claim 18 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the low tunnel barrier includes a tunnel barrier of less than 1.5 eV.

Claim 24

Dependent Claim 48 words

The electronic system of claim 18 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 25

Dependent Claim 65 words

The electronic system of claim 18 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 26

Dependent Claim 71 words

The electronic system of claim 18 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 27

Dependent Claim 34 words

The electronic system of claim 18 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

Claim 28

Dependent Claim 43 words

The electronic system of claim 18 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

Claim 29

Dependent Claim 72 words

The electronic system of claim 18 , wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 30

Dependent Claim 21 words

The electronic system of claim 26 , wherein the plurality of control gate lines are disposed vertically above the floating gates.

Claim 31

Independent Claim 221 words

A method for forming an array of DEAPROM memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 32

Independent Claim 221 words

A method for forming an array of DEAPROM memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 33

Dependent Claim 75 words

The method of claim 28 , wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 34

Dependent Claim 50 words

The method of claim 28 , wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier inter gate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 35

Dependent Claim 58 words

The method of claim 28 , wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein forming the low tunnel barrier intergate insulator includes forming a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.

Claim 36

Dependent Claim 69 words

The method of claim 28 , wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 37

Dependent Claim 70 words

The method of claim 28 , wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gales such that each control gate line addresses a floating gate on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 38

Dependent Claim 46 words

The method of claim 28 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.

Claim 39

Dependent Claim 62 words

The method of claim 28 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

Claim 40

Dependent Claim 72 words

The method of claim 28 , wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 41

Dependent Claim 34 words

The method of claim 36 , wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.

Claim 42

Dependent Claim 177 words

A memory array, comprising: a number of memory cells, wherein each memory cell includes: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the memory array, a number of control gate lines coupled to the control gates along a second selected direction in the memory array; a number of bitlines coupled to the second source/drain regions along a third selected direction in the memory array; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 43

Dependent Claim 177 words

A memory array, comprising: a number of memory cells, wherein each memory cell includes: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the memory array, a number of control gate lines coupled to the control gates along a second selected direction in the memory array; a number of bitlines coupled to the second source/drain regions along a third selected direction in the memory array; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 44

Dependent Claim 17 words

The memory array of claim 38 , wherein the memory cells include electronically alterable programmable read-only memory.

Claim 45

Dependent Claim 215 words

An array of memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 46

Dependent Claim 215 words

An array of memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 47

Dependent Claim 19 words

The array of memory cells of claim 40 , wherein the memory cells include electronically alterable programmable read-only memory.

Claim 48

Independent Claim 218 words

A method for forming an array of memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates lines arc separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 49

Independent Claim 218 words

A method for forming an array of memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates lines arc separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 50

Dependent Claim 19 words

The array of memory cells of claim 42 , wherein the memory cells include electronically alterable programmable read-only memory.

Claim 51

Dependent Claim 226 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried source/lines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of memory cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 52

Dependent Claim 226 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried source/lines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of memory cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 53

Dependent Claim 74 words

The memory array of claim 38 , wherein the low tunnel hairier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 54

Dependent Claim 47 words

The memory array of claim 38 , wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 55

Dependent Claim 47 words

The memory array of claim 38 , wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 56

Dependent Claim 41 words

The memory array of claim 38 , wherein the second selected direction and the third selected direction are parallel to one another and orthogonal to the first selected direction, and wherein the number of control gate lines serve as address lines.

Claim 57

Dependent Claim 41 words

The memory ray of claim 38 , wherein the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction, and wherein the number of control gate lines serve as address lines.

Claim 58

Dependent Claim 39 words

The memory ray of claim 38 , wherein the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction, and wherein the number of bitlines serve as address lines.

Claim 59

Dependent Claim 76 words

The array of memory cells of claim 40 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 60

Dependent Claim 49 words

The array of memory cells of claim 40 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 61

Dependent Claim 49 words

The array of memory cells of claim 40 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 62

Dependent Claim 67 words

The array of memory cells of claim 40 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 63

Dependent Claim 73 words

The array of memory cells of claim 40 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each french houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 64

Dependent Claim 36 words

The array of memory cells of claim 40 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

Claim 65

Dependent Claim 46 words

The array of memory cells of claim 40 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control gate lines.

Claim 66

Dependent Claim 74 words

The array of memory cells of claim 40 , wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 67

Dependent Claim 23 words

The may of memory cells of claim 58 , wherein the plurality of control gate lines are disposed vertically above the floating gates.

Claim 68

Dependent Claim 74 words

The electronic system of claim 44 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 69

Dependent Claim 46 words

The electronic system of claim 44 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the low tunnel harrier includes a tunnel barrier of less than 1.5 eV.

Claim 70

Dependent Claim 48 words

The electronic system of claim 44 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 71

Dependent Claim 65 words

The electronic system of claim 44 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gales, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 72

Dependent Claim 71 words

The electronic system of claim 44 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one On opposing sides of the french respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 73

Dependent Claim 34 words

The electronic system of claim 44 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

Claim 74

Dependent Claim 43 words

The electronic system of claim 38 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

Claim 75

Dependent Claim 72 words

The electronic system of claim 38 , wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 76

Dependent Claim 21 words

The electronic system of claim 67 , wherein the plurality of control gate lines arc disposed vertically above the floating gates.

Claim 77

Dependent Claim 75 words

The method of claim 42 , wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 78

Dependent Claim 49 words

The method of claim 42 , wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

Claim 79

Dependent Claim 58 words

The method of claim 42 , wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein forming the low tunnel barrier intergate insulator includes forming a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.

Claim 80

Dependent Claim 69 words

The method of claim 42 , wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 81

Dependent Claim 70 words

The method of claim 42 , wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gates such that each control gate line addresses a floating gate on opposing sides of the trench respectively and wherein the pair of control gate lines are separated by an insulator layer.

Claim 82

Dependent Claim 46 words

The method of claim 42 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.

Claim 83

Dependent Claim 62 words

The method of claim 42 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines arc disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

Claim 84

Dependent Claim 72 words

The method of claim 42 , wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 85

Dependent Claim 34 words

The method of claim 42 , wherein the forming the plurality of control gale lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.

Claim 86

Independent Claim 217 words

A method for forming an array of memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of busied sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the member of control gates along a second selected direction in the array of memory cells; separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 87

Independent Claim 217 words

A method for forming an array of memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of busied sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the member of control gates along a second selected direction in the array of memory cells; separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 88

Dependent Claim 19 words

The array of memory cells of claim 77 , wherein the memory cells include electronically alterable programmable read-only memory.

Claim 89

Independent Claim 234 words

A method for forming an electronic system, comprising: providing a memory device including an array of memory cells formed by: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars arid coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells separating the number of control gates lines from the floating gatos by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench; and connecting the memory device to a processor.

Claim 90

Independent Claim 234 words

A method for forming an electronic system, comprising: providing a memory device including an array of memory cells formed by: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars arid coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells separating the number of control gates lines from the floating gatos by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench; and connecting the memory device to a processor.

Claim 91

Dependent Claim 53 words

The method of claim 80 , wherein separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator includes separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2007-08-17	2008-02-16	2008-08-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2011-08-17	2012-02-16	2012-08-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2015-08-17	2016-02-16	2016-08-17	$7700.00	Window Closed / Lapsed

Integrated circuit memory device and method

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