US20040004247A1 — Memory utilizing oxide-nitride nanolaminates

Claim 1

Independent Claim 61 words

1 . A transistor, comprising: a first source/drain region a second source/drain region a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claim 2

Dependent Claim 61 words

1 . A transistor, comprising: a first source/drain region a second source/drain region a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claim 3

Dependent Claim 16 words

2 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include silicon nitride.

Claim 4

Dependent Claim 16 words

3 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include aluminum nitride.

Claim 5

Dependent Claim 16 words

4 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include gallium nitride.

Claim 6

Dependent Claim 17 words

5 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

Claim 7

Dependent Claim 17 words

6 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

Claim 8

Dependent Claim 17 words

7 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

Claim 9

Dependent Claim 17 words

8 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

Claim 10

Dependent Claim 17 words

9 . The transistor of claim 1 , wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

Claim 11

Dependent Claim 143 words

10 . A vertical multistate cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers adapted to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a sourceline coupled to the first source/drain region; a transmission line coupled to the second source/drain region; and wherein the MOSFET is a programmed MOSFET having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

Claim 12

Dependent Claim 143 words

10 . A vertical multistate cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers adapted to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a sourceline coupled to the first source/drain region; a transmission line coupled to the second source/drain region; and wherein the MOSFET is a programmed MOSFET having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

Claim 13

Dependent Claim 18 words

11 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include silicon nitride.

Claim 14

Dependent Claim 18 words

12 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include aluminum nitride.

Claim 15

Dependent Claim 18 words

13 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include gallium nitride.

Claim 16

Dependent Claim 19 words

14 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

Claim 17

Dependent Claim 19 words

15 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

Claim 18

Dependent Claim 19 words

16 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

Claim 19

Dependent Claim 19 words

17 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

Claim 20

Dependent Claim 19 words

18 . The vertical multistate cell of claim 10 , wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

Claim 21

Dependent Claim 34 words

19 . The vertical multistate cell of claim 10 , wherein the first source/drain region of the MOSFET includes a source region and the second source/drain region of the MOSFET includes a drain region.

Claim 22

Dependent Claim 41 words

20 . The vertical multistate cell of claim 19 , wherein the second voltage threshold region (Vt2) in the channel is adjacent the source region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the drain region.

Claim 23

Dependent Claim 20 words

21 . The multistate cell of claim 20 , wherein the Vt2 has a higher voltage threshold than the Vt1.

Claim 24

Dependent Claim 31 words

22 . The vertical multistate cell of claim 6 , wherein the number of charge levels trapped in the gate insulator adjacent the first source/drain region includes a trapped electron charge.

Claim 25

Dependent Claim 22 words

23 . The vertical multistate cell of claim 6 , wherein the gate insulator has a thickness of approximately 1-10 nanometers (nm).

Claim 26

Dependent Claim 173 words

24 . A vertical multistate cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate insulator wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and wherein the MOSFET is a programmed MOSFET having a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the drain region and a second voltage threshold region (Vt2) adjacent to the source region, the Vt2 having a greater voltage threshold than Vt1.

Claim 27

Dependent Claim 173 words

24 . A vertical multistate cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate insulator wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and wherein the MOSFET is a programmed MOSFET having a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the drain region and a second voltage threshold region (Vt2) adjacent to the source region, the Vt2 having a greater voltage threshold than Vt1.

Claim 28

Dependent Claim 18 words

25 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include silicon nitride.

Claim 29

Dependent Claim 18 words

26 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include aluminum nitride.

Claim 30

Dependent Claim 18 words

27 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include gallium nitride.

Claim 31

Dependent Claim 19 words

28 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

Claim 32

Dependent Claim 19 words

29 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

Claim 33

Dependent Claim 19 words

30 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

Claim 34

Dependent Claim 19 words

31 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

Claim 35

Dependent Claim 19 words

32 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

Claim 36

Dependent Claim 31 words

33 . The vertical multistate cell of claim 24 , wherein the oxide-nitride nanolaminate layers have atomic dimensions with precisely controlled interfaces and layer thickness formed by atomic layer deposition (ALD).

Claim 37

Dependent Claim 22 words

34 . The vertical multistate cell of claim 24 , wherein the gate insulator has a thickness of approximately 1-10 nanometers (nm).

Claim 38

Dependent Claim 192 words

35 . A transistor array, comprising: a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array; a number of word lines coupled to the gate of each transistor cell along columns of the memory array; a number of sourcelines, wherein the first source/drain region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells; and wherein at least one of transistor cells is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

Claim 39

Dependent Claim 192 words

35 . A transistor array, comprising: a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array; a number of word lines coupled to the gate of each transistor cell along columns of the memory array; a number of sourcelines, wherein the first source/drain region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells; and wherein at least one of transistor cells is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

Claim 40

Dependent Claim 17 words

36 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include silicon nitride.

Claim 41

Dependent Claim 17 words

37 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include aluminum nitride.

Claim 42

Dependent Claim 17 words

38 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include gallium nitride.

Claim 43

Dependent Claim 18 words

39 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

Claim 44

Dependent Claim 18 words

40 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

Claim 45

Dependent Claim 18 words

41 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

Claim 46

Dependent Claim 18 words

42 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

Claim 47

Dependent Claim 18 words

43 . The transistor array of claim 35 , wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

Claim 48

Dependent Claim 34 words

44 . The transistor array of claim 35 , wherein the one of a number of charge levels trapped in the gate insulator includes a charge adjacent to the source of approximately 100 electrons.

Claim 49

Dependent Claim 35 words

45 . The transistor array of claim 35 , wherein the first source/drain region of the transistor cell includes a source region and the second source/drain region of the transistor cell includes a drain region.

Claim 50

Dependent Claim 53 words

46 . The transistor array of claim 35 , wherein the second voltage threshold region (Vt2) in the channel is adjacent the first source/drain region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the second source/drain region, and wherein Vt2 has a higher voltage threshold than the Vt1.

Claim 51

Dependent Claim 25 words

47 . The transistor array of claim 21 , wherein the gate insulator of each transistor cell has a thickness of approximately 1-10 nanometers (nm).

Claim 52

Dependent Claim 39 words

48 . The transistor array of claim 21 , wherein the number of transistor cells extending from a substrate operate as equivalent to a transistor having a size equal to or than 1.0 lithographic feature squared (1F 2 ).

Claim 53

Dependent Claim 349 words

49 . A memory array, comprising: a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the drain region of each transistor along rows of the memory array; a number of word lines coupled to the gate of each transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of multistate cell transistors is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region of that transistor has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed transistor operates at reduced drain source current.

Claim 54

Dependent Claim 349 words

49 . A memory array, comprising: a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the drain region of each transistor along rows of the memory array; a number of word lines coupled to the gate of each transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of multistate cell transistors is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region of that transistor has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed transistor operates at reduced drain source current.

Claim 55

Dependent Claim 37 words

50 . The memory array of claim 49 , wherein the number of sourcelines formed in a bottom of the trenches between rows of the pillars include a doped region implanted in the bottom of the trench.

Claim 56

Dependent Claim 35 words

51 . The memory array of claim 49 , wherein the one of a number of charge levels trapped in the gate insulator includes a charge adjacent to the source region of approximately 100 electrons.

Claim 57

Dependent Claim 51 words

52 . The memory array of claim 49 , wherein the second voltage threshold region (Vt2) in the channel is adjacent the source region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the drain region, and wherein Vt2 has a higher voltage threshold than the Vt1.

Claim 58

Dependent Claim 26 words

53 . The memory array of claim 49 , wherein the gate insulator of each multistate cell transistor has a thickness of approximately 1-10 nanometers (nm).

Claim 59

Dependent Claim 17 words

54 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include silicon nitride.

Claim 60

Dependent Claim 17 words

55 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include aluminum nitride.

Claim 61

Dependent Claim 17 words

56 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include gallium nitride.

Claim 62

Dependent Claim 18 words

57 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

Claim 63

Dependent Claim 18 words

58 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

Claim 64

Dependent Claim 18 words

59 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

Claim 65

Dependent Claim 18 words

60 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

Claim 66

Dependent Claim 18 words

61 . The memory array of claim 49 , wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

Claim 67

Dependent Claim 36 words

62 . The memory array of claim 49 , wherein the wordline address decoder and the bitline address decoder each include conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO 2 ).

Claim 68

Dependent Claim 29 words

63 . The memory array of claim 49 , wherein the sense amplifier includes conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO 2 ).

Claim 69

Dependent Claim 147 words

64 . A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claim 70

Dependent Claim 147 words

64 . A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claim 71

Dependent Claim 18 words

65 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include silicon nitride.

Claim 72

Dependent Claim 18 words

66 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include aluminum nitride.

Claim 73

Dependent Claim 18 words

67 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include gallium nitride.

Claim 74

Dependent Claim 19 words

68 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

Claim 75

Dependent Claim 19 words

69 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

Claim 76

Dependent Claim 19 words

70 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

Claim 77

Dependent Claim 19 words

71 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

Claim 78

Dependent Claim 19 words

72 . The programmable logic array of claim 64 , wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

Claim 79

Dependent Claim 364 words

73 . An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes; a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the drain region of each transistor along rows of the memory array; a number of word lines coupled to the gate of each transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of multistate cell transistors is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region of that transistor has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed transistor operates at reduced drain source current.

Claim 80

Dependent Claim 364 words

73 . An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes; a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the drain region of each transistor along rows of the memory array; a number of word lines coupled to the gate of each transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of multistate cell transistors is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region of that transistor has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed transistor operates at reduced drain source current.

Claim 81

Dependent Claim 37 words

74 . The electronic system of claim 73 , wherein the number of sourcelines formed in a bottom of the trenches between rows of the pillars include a doped region implanted in the bottom of the trench.

Claim 82

Dependent Claim 35 words

75 . The electronic system of claim 73 , wherein the one of a number of charge levels trapped in the gate insulator includes a charge adjacent to the source region of approximately 100 electrons.

Claim 83

Dependent Claim 51 words

76 . The electronic system of claim 73 , wherein the second voltage threshold region (Vt2) in the channel is adjacent the source region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the drain region, and wherein Vt2 has a higher voltage threshold than the Vt1.

Claim 84

Dependent Claim 24 words

77 . The electronic system of claim 73 , wherein the gate insulator of each transistor has a thickness of approximately 10 nanometers (nm).

Claim 85

Dependent Claim 17 words

78 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include silicon nitride.

Claim 86

Dependent Claim 17 words

79 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include aluminum nitride.

Claim 87

Dependent Claim 17 words

80 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include gallium nitride.

Claim 88

Dependent Claim 18 words

81 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

Claim 89

Dependent Claim 18 words

82 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

Claim 90

Dependent Claim 18 words

83 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

Claim 91

Dependent Claim 18 words

84 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

Claim 92

Dependent Claim 18 words

85 . The electronic system of claim 73 , wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

Claim 93

Dependent Claim 33 words

86 . The electronic system of claim 73 , wherein each transistor operates as equivalent to a transistor having a size equal to or less than 1.0 lithographic feature squared (1F 2 ).

Claim 94

Dependent Claim 86 words

87 . The electronic system of claim 73 , wherein, in a read operation, a sourceline for two column adjacent pillars sharing a trench is coupled to a ground potential, the drain regions of the column adjacent pillars sharing a trench are precharged to a fractional voltage of VDD, and the gate for each of the column adjacent pillars sharing a trench is addressed such that a conductivity state of a multistate cell transistor can be compared to a conductivity state of a reference cell transistor.

Claim 95

Dependent Claim 70 words

88 . The electronic system of claim 73 , wherein, in a write operation, a sourceline for two column adjacent pillars sharing a trench is biased to a voltage higher than VDD, one of the drain regions of the column adjacent pillars sharing a trench is coupled to a ground potential, and the gate for each of the column adjacent pillars sharing a trench is addressed with a wordline potential.

Claim 96

Dependent Claim 239 words

89 . A method for operating a transistor array, comprising: programming one or more transistors in the array in a reverse direction, wherein each transistor includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the array includes a number of sourcelines coupled to the source regions of each transistor along rows in the array, and wherein the array includes a number of bitlines coupled to the drain region along rows in the array, and wherein programming the one or more transistors in the reverse direction includes: applying a first voltage potential to a drain region of the transistor; applying a second voltage potential to a source region of the transistor; applying a gate potential to a gate of the transistor; and wherein applying the first, second and gate potentials to the one or more transistors includes creating a hot electron injection into the gate insulator of the one or more transistors adjacent to the source region such that the one or more transistors become programmed transistors having one of a number of charge levels trapped in the gate insulator such that the programmed transistor operates at reduced drain source current in a forward direction.

Claim 97

Dependent Claim 239 words

89 . A method for operating a transistor array, comprising: programming one or more transistors in the array in a reverse direction, wherein each transistor includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the array includes a number of sourcelines coupled to the source regions of each transistor along rows in the array, and wherein the array includes a number of bitlines coupled to the drain region along rows in the array, and wherein programming the one or more transistors in the reverse direction includes: applying a first voltage potential to a drain region of the transistor; applying a second voltage potential to a source region of the transistor; applying a gate potential to a gate of the transistor; and wherein applying the first, second and gate potentials to the one or more transistors includes creating a hot electron injection into the gate insulator of the one or more transistors adjacent to the source region such that the one or more transistors become programmed transistors having one of a number of charge levels trapped in the gate insulator such that the programmed transistor operates at reduced drain source current in a forward direction.

Claim 98

Dependent Claim 29 words

90 . The method of claim 89 , wherein applying a first voltage potential to the drain region of the transistor includes grounding the drain region of the transistor.

Claim 99

Dependent Claim 30 words

91 . The method of claim 90 , wherein applying a second voltage potential to the source region includes applying a high voltage potential (VDD) to a sourceline coupled thereto.

Claim 100

Dependent Claim 43 words

92 . The method of claim 91 , wherein applying a gate potential to the gate of the transistor includes applying a gate potential to the gate in order to create a conduction channel between the source and drain regions of the transistor.

Claim 101

Dependent Claim 97 words

93 . The method of claim 89 , wherein the method further includes reading one or more transistors in the array by operating an addressed transistor in a forward direction, wherein operating the transistor in the forward direction includes: grounding the source region for the addressed transistor; precharging the drain region for the addressed transistor to a fractional voltage of VDD; and applying a gate potential of approximately 1.0 Volt to the gate for the addressed transistor such that a conductivity state of the addressed transistor can be compared to a conductivity state of a reference cell.

Claim 102

Dependent Claim 56 words

94 . The method of claim 89 , wherein in creating a hot electron injection into the gate insulator of the one or more transistors adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region.

Claim 103

Dependent Claim 399 words

95 . A method for multistate memory, comprising: writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes; biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD; grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFETs becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction; reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes; grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench; precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD; and applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell.

Claim 104

Dependent Claim 399 words

95 . A method for multistate memory, comprising: writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes; biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD; grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFETs becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction; reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes; grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench; precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD; and applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell.

Claim 105

Dependent Claim 59 words

96 . The method of claim 95 , wherein creating a hot electron injection into the gate insulator of the addressed MOSFET adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region, wherein Vt2 is greater that Vt1.

Claim 106

Dependent Claim 87 words

97 . The method of claim 95 , wherein reading one or more vertical MOSFETs in the DRAM array in a forward direction includes using a sense amplifier to detect whether an addressed vertical MOSFET is a programmed vertical MOSFET, wherein a programmed vertical MOSFET will not conduct, and wherein an unprogrammed vertical MOSFET addressed over approximately 10 ns will conduct a current of approximately 12.5 μA such that the method includes detecting an integrated drain current having a charge of 800,000 electrons using the sense amplifier.

Claim 107

Dependent Claim 37 words

98 . The method of claim 95 , wherein in creating a hot electron injection into the gate insulator of an addressed vertical MOSFET includes changing a threshold voltage for the vertical MOSFET by approximately 0.5 Volts.

Claim 108

Dependent Claim 44 words

99 . The method of claim 95 , wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 10 12 electrons/cm 2 .

Claim 109

Dependent Claim 41 words

100 . The method of claim 95 , wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 100 electrons.

Claim 110

Dependent Claim 55 words

101 . The method of claim 95 , wherein the method further includes using the vertical MOSFET as active device with gain, and wherein reading a programmed vertical MOSFET includes providing an amplification of a stored charge in the gate insulator from 100 to 800,000 electrons over a read address period of approximately 10 ns.

Claim 111

Dependent Claim 68 words

102 . A method for forming a transistor, comprising: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a gate insulator opposing the channel region, wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers which trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; and forming a gate opposing the gate insulator.

Claim 112

Dependent Claim 68 words

102 . A method for forming a transistor, comprising: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a gate insulator opposing the channel region, wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers which trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; and forming a gate opposing the gate insulator.

Claim 113

Dependent Claim 21 words

103 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of silicon nitride.

Claim 114

Dependent Claim 21 words

104 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of aluminum nitride.

Claim 115

Dependent Claim 21 words

105 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium nitride.

Claim 116

Dependent Claim 22 words

106 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium aluminum nitride.

Claim 117

Dependent Claim 22 words

107 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tantalum aluminum nitride.

Claim 118

Dependent Claim 22 words

108 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium silicon nitride.

Claim 119

Dependent Claim 22 words

109 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium aluminum nitride.

Claim 120

Dependent Claim 22 words

110 . The method of claim 102 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tungsten aluminum nitride.

Claim 121

Dependent Claim 319 words

111 . A method for forming a multistate memory array, comprising: forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench, and wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the gate of each transistor along columns of the memory array; forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; and wherein the number of vertical pillars can be programmed in a reverse direction to have a one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address.

Claim 122

Dependent Claim 319 words

111 . A method for forming a multistate memory array, comprising: forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench, and wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the gate of each transistor along columns of the memory array; forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; and wherein the number of vertical pillars can be programmed in a reverse direction to have a one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address.

Claim 123

Dependent Claim 37 words

112 . The method of claim 111 , wherein forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trench.

Claim 124

Dependent Claim 41 words

113 . The method of claim 111 , wherein, in forming a gate insulator above the channel region in the trenches along rows of pillars, the method includes forming a gate insulator having a thickness of at least 10 nanometers (nm).

Claim 125

Dependent Claim 21 words

114 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of silicon nitride.

Claim 126

Dependent Claim 21 words

115 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of aluminum nitride.

Claim 127

Dependent Claim 21 words

116 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium nitride.

Claim 128

Dependent Claim 22 words

117 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium aluminum nitride.

Claim 129

Dependent Claim 22 words

118 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tantalum aluminum nitride.

Claim 130

Dependent Claim 22 words

119 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium silicon nitride.

Claim 131

Dependent Claim 22 words

120 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium aluminum nitride.

Claim 132

Dependent Claim 22 words

121 . The method of claim 111 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tungsten aluminum nitride.

Memory utilizing oxide-nitride nanolaminates

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