US6541816B2
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Planar structure for non-volatile memory devices
Assignee: Longitude Flash Memory Solutions Ltd
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Filing: 2001-06-27
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Granted: 2003-04-01
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Expires: 2021-06-27
Abstract
Abstract One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.
Inventors
- 👤 Mark T. Ramsbey
- 👤 Jean Y. Yang
- 👤 Hidehiko Shiraiwa
- 👤 Michael A. Van Buskirk
- 👤 David M. Rogers
- 👤 Ravi S. Sunkavalli
- 👤 Janet S. Wang
- 👤 Narbeh Derhacobian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:08
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10B43/40; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/954; Y10S438/981
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
98 words
A non-volatile semiconductor memory device, comprising: a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the entire core region of the substrate wherein the charge trapping dielectric in the core region is substantially planar; a gate dielectric in the periphery region of the substrate; buried bitlines directly under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, with the proviso that the core region does not comprise bitline oxides and the proviso that the core region does not comprise LOCOS.
Claim 2
Dependent Claim
98 words
A non-volatile semiconductor memory device, comprising: a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the entire core region of the substrate wherein the charge trapping dielectric in the core region is substantially planar; a gate dielectric in the periphery region of the substrate; buried bitlines directly under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, with the proviso that the core region does not comprise bitline oxides and the proviso that the core region does not comprise LOCOS.
Claim 3
Dependent Claim
69 words
The memory device according to claim 1 , wherein the charge trapping dielectric comprises at least one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 4
Dependent Claim
32 words
The memory device according to claim 1 , wherein the charge trapping dielectric comprises an ONO dielectric comprising at least one of a nitrided oxide layer and a silicon-rich silicon nitride layer.
Claim 5
Dependent Claim
15 words
The memory device according to claim 1 , wherein the gate dielectric comprises silicon dioxide.
Claim 6
Dependent Claim
21 words
The memory device according to claim 1 , wherein the buried bitlines comprise at least one of arsenic, boron, and phosphorus.
Claim 7
Dependent Claim
21 words
The memory device according to claim 1 , wherein the wordlines comprise at least one of polysilicon and doped amorphous silicon.
Claim 8
Dependent Claim
24 words
The memory device according to claim 1 , wherein the charge trapping dielectric has a thickness from about 75 Å to about 300 Å.
Claim 9
Dependent Claim
93 words
A non-volatile semiconductor memory device, comprising: a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the entire core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines directly under the charge trapping dielectric in the core region; and substantially planar wordlines having a substantially uniform thickness over the charge trapping dielectric in the core region, with the proviso that the core region does not comprise bitline oxides and the proviso that the core region does not comprise LOCOS.
Claim 10
Dependent Claim
93 words
A non-volatile semiconductor memory device, comprising: a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the entire core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines directly under the charge trapping dielectric in the core region; and substantially planar wordlines having a substantially uniform thickness over the charge trapping dielectric in the core region, with the proviso that the core region does not comprise bitline oxides and the proviso that the core region does not comprise LOCOS.
Claim 11
Dependent Claim
27 words
The memory device according to claim 8 , wherein the gate dielectric in the periphery region has a thickness from about 30 Å to about 300 Å.
Claim 12
Dependent Claim
35 words
The memory device according to claim 8 , wherein the buried bitlines comprise at least one of arsenic, boron, and phosphorus at a dosage from about 1×10 14 to about 1×10 16 atoms/cm 2 .
Claim 13
Dependent Claim
67 words
The memory device according to claim 8 , wherein the charge trapping dielectric comprises one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 14
Dependent Claim
32 words
The memory device according to claim 8 , wherein the charge trapping dielectric comprises an ONO dielectric comprising at least one of a nitrided oxide layer and a silicon-rich silicon nitride layer.
Claim 15
Dependent Claim
96 words
A SONOS flash memory device, comprising: a substrate, the substrate having a core region and a periphery region; an ONO charge trapping dielectric over the entire core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines directly under the ONO charge trapping dielectric in the core region; and substantially planar wordlines having a substantially uniform thickness over the ONO charge trapping dielectric in the core region, with the proviso that the core region does not comprise bitline oxides and the proviso that the core region does not comprise LOCOS.
Claim 16
Dependent Claim
96 words
A SONOS flash memory device, comprising: a substrate, the substrate having a core region and a periphery region; an ONO charge trapping dielectric over the entire core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines directly under the ONO charge trapping dielectric in the core region; and substantially planar wordlines having a substantially uniform thickness over the ONO charge trapping dielectric in the core region, with the proviso that the core region does not comprise bitline oxides and the proviso that the core region does not comprise LOCOS.
Claim 17
Dependent Claim
24 words
The memory device according to claim 13 , wherein the buried bitlines are formed by implanting at least one of arsenic, boron, and phosphorus.
Claim 18
Dependent Claim
29 words
The memory device according to claim 13 , wherein the ONO charge trapping dielectric comprises at least one of a nitrided oxide layer and a silicon-rich silicon nitride layer.
Claim 19
Dependent Claim
23 words
The memory device according to claim 13 , wherein the buried bitlines have a width from about 0.18 μm to about 1 μm.
Claim 20
Dependent Claim
22 words
The memory device according to claim 13 , wherein the buried bitlines comprise at least one of an n+ and p+ dopant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-31 | 2006-09-30 | 2007-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-31 | 2010-09-30 | 2011-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-31 | 2014-09-30 | 2015-04-01 | $7700.00 | Window Closed / Lapsed |