US5907171A
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Method of making floating-gate memory-cell array with digital logic transistors
Assignee: Texas Instruments Inc
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Filing: 1997-11-25
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Granted: 1999-05-25
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Expires: 2017-11-25
Abstract
Abstract A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in ultra-violet erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.
Inventors
- 👤 Giovani Santin
- 👤 Giulio Marotta
- 👤 Michael C. Smayling
- 👤 Misako A. Matsuoka
- 👤 Satoru Fukawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:09
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
144 words
A nonvolatile, floating-gate memory with logic transistors, comprising: a semiconductor body having doping of a first conductivity-type; at least first and second opposite-conductivity-type diffusion regions having a first depth in said semiconductor body, said opposite-conductivity-type diffusion regions having doping primarily of a second conductivity-type opposite said first conductivity-type; at least first and second same-conductivity-type diffusion regions having a second depth in said semiconductor body, said first and second same-conductivity-type diffusion regions having doping primarily of said first conductivity-type, said first same-conductivity-type diffusion region encased by said first opposite conductivity-type diffusion region, said second same-conductivity-type diffusion region separated on said substrate from said first and second opposite-conductivity-type diffusion regions; and at least one floating-gate memory cell in said first same-conductivity-type diffusion region, at least one high-voltage logic transistor in said second opposite-conductivity-type region, and at least one low-voltage logic transistor in said second same-conductivity-type region.
Claim 2
Dependent Claim
144 words
A nonvolatile, floating-gate memory with logic transistors, comprising: a semiconductor body having doping of a first conductivity-type; at least first and second opposite-conductivity-type diffusion regions having a first depth in said semiconductor body, said opposite-conductivity-type diffusion regions having doping primarily of a second conductivity-type opposite said first conductivity-type; at least first and second same-conductivity-type diffusion regions having a second depth in said semiconductor body, said first and second same-conductivity-type diffusion regions having doping primarily of said first conductivity-type, said first same-conductivity-type diffusion region encased by said first opposite conductivity-type diffusion region, said second same-conductivity-type diffusion region separated on said substrate from said first and second opposite-conductivity-type diffusion regions; and at least one floating-gate memory cell in said first same-conductivity-type diffusion region, at least one high-voltage logic transistor in said second opposite-conductivity-type region, and at least one low-voltage logic transistor in said second same-conductivity-type region.
Claim 3
Dependent Claim
36 words
The floating-gate memory with logic transistors of claim 1, wherein said semiconductor body is silicon of P conductivity-type, said first diffusion region is primarily of N conductivity-type, said second diffusion region is primarily of P conductivity-type.
Claim 4
Dependent Claim
40 words
The floating-gate memory with logic transistors of claim 1, wherein during erasing operation said first opposite-conductivity-type diffusion region and said first same conductivity-type diffusion region are connected to a positive potential with respect to the potential of said semiconductor body.
Claim 5
Dependent Claim
22 words
The floating-gate memory with logic transistors of claim 1, wherein Fowler-Nordheim tunnelling is used to erase said floating gate of memory cell.
Claim 6
Dependent Claim
26 words
The floating-gate memory with logic transistors of claim 1, wherein said floating-gate memory cell is part of an X-cell memory array having single-dopant sources and drains.
Claim 7
Dependent Claim
32 words
The floating-gate memory with logic transistors of claim 1, further including field oxide regions on the surface of said semiconductor substrate, said field oxide regions over the edges of said diffusion regions.
Claim 8
Dependent Claim
43 words
The floating-gate memory with logic transistors of claim 1, further including field oxide regions on the surface of said semiconductor substrate, said field oxide regions over the edges of said diffusion regions and within said diffusion regions surrounding at least one connection point.
Claim 9
Dependent Claim
54 words
The floating-gate memory with logic transistors of claim 1, further including field oxide regions on the surface of said semiconductor substrate, said field oxide regions surrounding connection points to said diffusion regions, said first opposite-conductivity-type diffusion region and said first same-conductivity-type diffusion regions having multiple connection points at the periphery of said diffusion regions.
Claim 10
Dependent Claim
29 words
The floating-gate memory with logic transistors of claim 1, further including diffused contacts in said first same-conductivity-type diffusion region, wherein said diffused contacts include additional doping of said same-conductivity-type.
Claim 11
Dependent Claim
29 words
The floating-gate memory with logic transistors of claim 1, further including diffused contacts in said first same conductivity-type diffusion region, wherein said diffused contacts are connected to doped polysilicon.
References Cited (Backward Citations)
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