Semiconductor memory device and a method for producing the same

Claim 1

A method for producing a semiconductor memory device comprising the steps of: forming a first insulating film on a conductive silicon substrate in which a plurality of reverse conductive wells and a plurality of element separation regions are formed; forming a first polysilicon layer on the first insulating film; patterning the first polysilicon layer to form a floating gate electrode layer of a non-volatile memory element and a transistor gate electrode layer with a breakdown-voltage of 20 V or less; forming a second insulating film on the silicon substrate; forming a second polysilicon layer on the second insulating film; patterning the second polysilicon layer to form a logic electrode layer, a transfer gate electrode layer of a volatile memory element, a driver electrode layer, and a control gate electrode layer of a non-volatile memory element; forming a third insulating film on the silicon substrate; forming a third polysilicon layer on the third insulating film; and patterning the third polysilicon layer to form a charge storage electrode layer of a volatile memory element so that the charge storage electrode layer is partly disposed on the transfer gate electrode layer with the third insulating film sandwiched there-between.

Claim 2

A method for producing a semiconductor memory device comprising the steps of: forming a first insulating film on a conductive silicon substrate in which a plurality of reverse conductive wells and a plurality of element separation regions are formed; forming a first polysilicon layer on the first insulating film; patterning the first polysilicon layer to form a floating gate electrode layer of a non-volatile memory element and a transistor gate electrode layer with a breakdown-voltage of 20 V or less; forming a second insulating film on the silicon substrate; forming a second polysilicon layer on the second insulating film; patterning the second polysilicon layer to form a logic electrode layer, a transfer gate electrode layer of a volatile memory element, a driver electrode layer, and a control gate electrode layer of a non-volatile memory element; forming a third insulating film on the silicon substrate; forming a third polysilicon layer on the third insulating film; and patterning the third polysilicon layer to form a charge storage electrode layer of a volatile memory element so that the charge storage electrode layer is partly disposed on the transfer gate electrode layer with the third insulating film sandwiched there-between.