US6406960B1
Expired / Lapsed
US
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Process for fabricating an ONO structure having a silicon-rich silicon nitride layer
Assignee: Monterey Research LLC
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Filing: 1999-10-25
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Granted: 2002-06-18
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Expires: 2019-10-25
Abstract
Abstract A process for fabricating an ONO layer in a non-volatile memory device including the steps of forming a first silicon oxide layer, a silicon-rich silicon nitride layer and a second silicon oxide layer. The silicon-rich silicon nitride layer is formed by either a PECVD process, an LPCVD, or an RTCVD process. The silicon-rich silicon nitride layer effectively holds electrical charge making the ONO layer particularly useful as a floating gate electrode in a two-bit EEPROM device.
Inventors
- 👤 Dawn M. Hopper
- 👤 David K. Foote
- 👤 Bharath Rangarajan
- 👤 Arvind Halliyal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/6891; H10D30/6893; H10D64/00; H10D64/01; H10D64/031; H10D64/035; Y; Y10; Y10S; Y10S438/00; Y10S438/954
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
90 words
A process for fabricating an ONO layer in a non-volatile memory device comprising: providing a semiconductor substrate; forming a first silicon oxide layer overlying the semiconductor substrate; forming a silicon-rich silicon nitride layer overlying the first silicon oxide layer using a RTCVD process, the RTCVD process comprising depositing the silicon nitride layer using an ammonia flow rate of about 0.5 slpm to about 1.5 slpm and a silane flow rate of about 200 sccm to about 350 sccm; and forming a second silicon oxide layer overlying the silicon nitride layer.
Claim 2
Dependent Claim
90 words
A process for fabricating an ONO layer in a non-volatile memory device comprising: providing a semiconductor substrate; forming a first silicon oxide layer overlying the semiconductor substrate; forming a silicon-rich silicon nitride layer overlying the first silicon oxide layer using a RTCVD process, the RTCVD process comprising depositing the silicon nitride layer using an ammonia flow rate of about 0.5 slpm to about 1.5 slpm and a silane flow rate of about 200 sccm to about 350 sccm; and forming a second silicon oxide layer overlying the silicon nitride layer.
Claim 3
Dependent Claim
21 words
The process of claim 1 , wherein forming a second silicon oxide layer comprises thermal oxidation of the silicon nitride layer.
Claim 4
Dependent Claim
150 words
A process for fabricating a stacked-gate structure including an ONO floating-gate electrode in a two-bit EEPROM device comprising: providing a semiconductor substrate having a first bit-line oxide layer and a second bit-line oxide layer therein separated by a substrate surface region; forming an ONO layer on the substrate surface region, wherein the ONO layer includes a first silicon oxide layer, a silicon rich silicon nitride layer, and second silicon oxide layer, the silicon rich silicon nitride layer formed by a RTCVD process, the RTCVD process comprising depositing the silicon nitride layer using an ammonia flow rate of about 0.5 slpm to about 1.5 slpm and a silane flow rate of about 200 sccm to about 350 sccm; depositing a gate electrode layer overlying the ONO layer; and forming a stacked-gate structure on the substrate surface region, wherein the stacked-gate structure includes a control-gate electrode overlying an ONO floating gate electrode.
Claim 5
Dependent Claim
150 words
A process for fabricating a stacked-gate structure including an ONO floating-gate electrode in a two-bit EEPROM device comprising: providing a semiconductor substrate having a first bit-line oxide layer and a second bit-line oxide layer therein separated by a substrate surface region; forming an ONO layer on the substrate surface region, wherein the ONO layer includes a first silicon oxide layer, a silicon rich silicon nitride layer, and second silicon oxide layer, the silicon rich silicon nitride layer formed by a RTCVD process, the RTCVD process comprising depositing the silicon nitride layer using an ammonia flow rate of about 0.5 slpm to about 1.5 slpm and a silane flow rate of about 200 sccm to about 350 sccm; depositing a gate electrode layer overlying the ONO layer; and forming a stacked-gate structure on the substrate surface region, wherein the stacked-gate structure includes a control-gate electrode overlying an ONO floating gate electrode.
Claim 6
Dependent Claim
26 words
The process of claim 3 , wherein forming an ONO layer comprises forming a second silicon oxide layer by thermal oxidation of the silicon nitride layer.
Claim 7
Dependent Claim
124 words
A process for fabricating a stacked-gate in a non-volatile memory device comprising: providing a semiconductor substrate having a silicon surface region; forming a first dielectric layer overlying the semiconductor substrate; forming a floating-gate layer overlying the first dielectric layer; forming an ONO layer overlying the floating gate layer, wherein the ONO layer includes a silicon rich silicon nitride layer formed by a RTCVD process, the RTCVD process comprising depositing the silicon nitride layer using an ammonia flow rate of about 0.5 slpm to about 1.5 slpm and a silane flow rate of about 200 sccm to about 350 sccm; forming a control-gate layer overlying the ONO layer; and patterning the control-gate layer, the ONO layer, and the floating-gate layer to form a stacked-gate structure.
Claim 8
Dependent Claim
124 words
A process for fabricating a stacked-gate in a non-volatile memory device comprising: providing a semiconductor substrate having a silicon surface region; forming a first dielectric layer overlying the semiconductor substrate; forming a floating-gate layer overlying the first dielectric layer; forming an ONO layer overlying the floating gate layer, wherein the ONO layer includes a silicon rich silicon nitride layer formed by a RTCVD process, the RTCVD process comprising depositing the silicon nitride layer using an ammonia flow rate of about 0.5 slpm to about 1.5 slpm and a silane flow rate of about 200 sccm to about 350 sccm; forming a control-gate layer overlying the ONO layer; and patterning the control-gate layer, the ONO layer, and the floating-gate layer to form a stacked-gate structure.
Claim 9
Dependent Claim
26 words
The process of claim 5 , wherein forming an ONO layer comprises forming a second silicon oxide layer by thermal oxidation of the silicon nitride layer.
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