US6063666A
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RTCVD oxide and N2 O anneal for top oxide of ONO film
Assignee: Monterey Research LLC
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Filing: 1998-06-16
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Granted: 2000-05-16
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Expires: 2018-06-16
Abstract
Abstract In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780° C. to about 820° C. using SiH 4 and N 2 O and annealing in an N 2 O atmosphere a temperature from about 980° C. to about 1020° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structure, thereby forming at least one memory cell.
Inventors
- 👤 Kent Kuohua Chang
- 👤 David Chi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:45
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01344; H10D64/01346; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/693; H10P14/65; H10P14/6516; H10P14/6529; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; Y; Y10; Y10S; Y10S438/00; Y10S438/954
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
185 words
A method of forming a flash memory cell, comprising: forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780° C. to about 820° C. using SiH 4 and N 2 O and annealing in an N 2 O atmosphere a temperature from about 980° C. to about 1020° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structure, thereby forming at least one memory cell.
Claim 2
Independent Claim
185 words
A method of forming a flash memory cell, comprising: forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780° C. to about 820° C. using SiH 4 and N 2 O and annealing in an N 2 O atmosphere a temperature from about 980° C. to about 1020° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structure, thereby forming at least one memory cell.
Claim 3
Dependent Claim
25 words
The method of claim 1, wherein the rapid thermal chemical vapor deposition is conducted under a pressure from about 1 Torr to about 10 Torr.
Claim 4
Dependent Claim
25 words
The method of claim 1, wherein the rapid thermal chemical vapor deposition is conducted under a pressure from about 2 Torr to about 5 Torr.
Claim 5
Dependent Claim
25 words
The method of claim 1, wherein the rapid thermal chemical vapor deposition is conducted at a temperature from about 790° C. to about 810° C.
Claim 6
Dependent Claim
26 words
The method of claim 1, wherein the annealing in the N 2 O atmosphere is conducted a temperature from about 990° C. to about 1010° C.
Claim 7
Dependent Claim
48 words
The method of claim 1, wherein the rapid thermal chemical vapor deposition is conducted using a gas flow comprising from about 0.1% to about 5% N 2 O, from about 5% to about 15% SiH 4 , and from about 80% to about 98% of a carrier gas.
Claim 8
Dependent Claim
11 words
The method of claim 6, wherein the carrier gas comprises argon.
Claim 9
Independent Claim
75 words
A method of forming an ONO insulating layer for a flash memory cell, comprising: depositing a first oxide layer; depositing a nitride layer; and depositing a second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780° C. to about 820° C. using SiH 4 and N 2 O and annealing the second oxide layer in an N 2 O atmosphere a temperature from about 980° C. to about 1020° C.
Claim 10
Independent Claim
75 words
A method of forming an ONO insulating layer for a flash memory cell, comprising: depositing a first oxide layer; depositing a nitride layer; and depositing a second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780° C. to about 820° C. using SiH 4 and N 2 O and annealing the second oxide layer in an N 2 O atmosphere a temperature from about 980° C. to about 1020° C.
Claim 11
Dependent Claim
21 words
The method of claim 8, wherein the second oxide layer has a thickness from about 30 Å to about 50 Å.
Claim 12
Dependent Claim
20 words
The method of claim 8, wherein the nitride layer has a thickness from about 70 Å to about 90 Å.
Claim 13
Dependent Claim
19 words
The method of claim 8, wherein the N 2 O atmosphere comprises at least about 95% N 2 O.
Claim 14
Dependent Claim
36 words
The method of claim 8, wherein the rapid thermal chemical vapor deposition is conducted at a temperature from about 790° C. to about 810° C. and a pressure from about 2 Torr to about 5 Torr.
Claim 15
Dependent Claim
48 words
The method of claim 8, wherein the rapid thermal chemical vapor deposition is conducted using a gas flow comprising from about 0.2% to about 2% N 2 O, from about 7% to about 13% SiH 4 , and from about 85% to about 95% of a carrier gas.
Claim 16
Independent Claim
131 words
A method of decreasing charge leakage from a floating gate to a control gate in a flash memory cell comprising a substrate, a tunnel oxide over the substrate, the floating gate over the tunnel oxide, an ONO insulating layer over the floating gate, and the control gate over the ONO insulating layer, wherein the ONO insulating layer comprises a first oxide layer over the floating gate, a nitride layer over the first oxide layer and a second oxide layer over the nitride layer, comprising: forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 790° C. to about 810° C. using SiH 4 and N 2 O; and annealing in an N 2 O atmosphere a temperature from about 990° C. to about 1010° C.
Claim 17
Independent Claim
131 words
A method of decreasing charge leakage from a floating gate to a control gate in a flash memory cell comprising a substrate, a tunnel oxide over the substrate, the floating gate over the tunnel oxide, an ONO insulating layer over the floating gate, and the control gate over the ONO insulating layer, wherein the ONO insulating layer comprises a first oxide layer over the floating gate, a nitride layer over the first oxide layer and a second oxide layer over the nitride layer, comprising: forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 790° C. to about 810° C. using SiH 4 and N 2 O; and annealing in an N 2 O atmosphere a temperature from about 990° C. to about 1010° C.
Claim 18
Dependent Claim
21 words
The method of claim 14, wherein the second oxide layer has a thickness from about 35 Å to about 45 Å.
Claim 19
Dependent Claim
25 words
The method of claim 14, wherein the rapid thermal chemical vapor deposition is conducted under a pressure from about 1 Torr to about 10 Torr.
Claim 20
Dependent Claim
25 words
The method of claim 14, wherein the rapid thermal chemical vapor deposition is conducted under a pressure from about 2 Torr to about 5 Torr.
Claim 21
Dependent Claim
48 words
The method of claim 14, wherein the rapid thermal chemical vapor deposition is conducted using a gas flow comprising from about 0.1% to about 5% N 2 O, from about 5% to about 15% SiH 4 , and from about 80% to about 98% of a carrier gas.
Claim 22
Dependent Claim
48 words
The method of claim 14, wherein the rapid thermal chemical vapor deposition is conducted using a gas flow comprising from about 0.2% to about 2% N 2 O, from about 7% to about 13% SiH 4 , and from about 85% to about 95% of a carrier gas.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |