US6570787B1
Expired / Lapsed
US
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Programming with floating source for low power, low leakage and high density flash memory devices
Assignee: Monterey Research LLC
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Filing: 2002-04-19
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Granted: 2003-05-27
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Expires: 2022-04-19
Abstract
Abstract The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.
Inventors
- 👤 Zhigang Wang
- 👤 Nian Yang
- 👤 Xin Guo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:29
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
107 words
A flash memory device, comprising: a plurality of flash memory cells arranged in a NOR type configuration, wherein the flash memory cells are arranged in rows and columns corresponding to word lines and bit lines, respectively, and wherein each of the plurality of flash memory cells have a source terminal coupled together to form a common source; and a common source selection component coupled between the common source and a predetermined potential, wherein the common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate the common source from the predetermined potential in a second state.
Claim 2
Dependent Claim
107 words
A flash memory device, comprising: a plurality of flash memory cells arranged in a NOR type configuration, wherein the flash memory cells are arranged in rows and columns corresponding to word lines and bit lines, respectively, and wherein each of the plurality of flash memory cells have a source terminal coupled together to form a common source; and a common source selection component coupled between the common source and a predetermined potential, wherein the common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate the common source from the predetermined potential in a second state.
Claim 3
Dependent Claim
48 words
The flash memory device of claim 1 , further comprising a common source control circuit operable to receive one or more input signals indicative of a mode of operation and output a control signal to the common source selection component based on the one or more input signals.
Claim 4
Dependent Claim
54 words
The flash memory device of claim 2 , wherein the common source control circuit is further operable to output the control signal to force the common source selection component to the second state when the one or more input signals indicate a program mode, thereby electrically isolating the common source from the predetermined potential.
Claim 5
Dependent Claim
29 words
The flash memory device of claim 2 , wherein the one or more control signals comprise a program mode signal, a read mode signal, and an erase mode signal.
Claim 6
Dependent Claim
32 words
The flash memory device of claim 1 , wherein the common source selection component comprises a transistor which is substantially on in the first state and substantially off in the second state.
Claim 7
Dependent Claim
36 words
The flash memory device of claim 5 , wherein the transistor comprises an NMOS transistor operable to substantially turn on when the control signal is high and substantially turn off when the control signal is low.
Claim 8
Dependent Claim
18 words
The flash memory device of claim 1 , wherein the predetermined voltage potential comprises a circuit ground potential.
Claim 9
Dependent Claim
126 words
A flash memory device, comprising: a plurality of bit lines, wherein each of the bits lines comprise a plurality of flash memory cells having a drain terminal coupled to its respective bit line, and a source terminal coupled together to form a common source; a plurality of word lines, wherein each of the word lines traverse the bit lines, and couple to a control gate terminal of flash memory cells associated with the traversed bit lines, respectively; a common source selection component coupled between the common source and a predetermined potential, wherein the common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate the common source from the predetermined potential in a second state.
Claim 10
Dependent Claim
126 words
A flash memory device, comprising: a plurality of bit lines, wherein each of the bits lines comprise a plurality of flash memory cells having a drain terminal coupled to its respective bit line, and a source terminal coupled together to form a common source; a plurality of word lines, wherein each of the word lines traverse the bit lines, and couple to a control gate terminal of flash memory cells associated with the traversed bit lines, respectively; a common source selection component coupled between the common source and a predetermined potential, wherein the common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate the common source from the predetermined potential in a second state.
Claim 11
Dependent Claim
48 words
The flash memory device of claim 8 , further comprising a common source control circuit operable to receive one or more input signals indicative of a mode of operation and output a control signal to the common source selection component based on the one or more input signals.
Claim 12
Dependent Claim
54 words
The flash memory device of claim 9 , wherein the common source control circuit is further operable to output the control signal to force the common source selection component to the second state when the one or more input signals indicate a program mode, thereby electrically isolating the common source from the predetermined potential.
Claim 13
Dependent Claim
29 words
The flash memory device of claim 9 , wherein the one or more control signals comprise a program mode signal, a read mode signal, and an erase mode signal.
Claim 14
Dependent Claim
32 words
The flash memory device of claim 8 , wherein the common source selection component comprises a transistor which is substantially on in the first state and substantially off in the second state.
Claim 15
Dependent Claim
36 words
The flash memory device of claim 12 , wherein the transistor comprises an NMOS transistor operable to substantially turn on when the control signal is high and substantially turn off when the control signal is low.
Claim 16
Dependent Claim
18 words
The flash memory device of claim 8 , wherein the predetermined voltage potential comprises a circuit ground potential.
Claim 17
Dependent Claim
80 words
A flash memory device, comprising: a plurality of flash memory cells arranged in a NOR type configuration, wherein the flash memory cells are arranged in rows and columns corresponding to word lines and bit lines, respectively, and wherein each of the plurality of flash memory cells have a source terminal coupled together to form a common source; and means for electrically isolating the common source from a predetermined potential based on a mode of operation of the flash memory device.
Claim 18
Dependent Claim
80 words
A flash memory device, comprising: a plurality of flash memory cells arranged in a NOR type configuration, wherein the flash memory cells are arranged in rows and columns corresponding to word lines and bit lines, respectively, and wherein each of the plurality of flash memory cells have a source terminal coupled together to form a common source; and means for electrically isolating the common source from a predetermined potential based on a mode of operation of the flash memory device.
Claim 19
Dependent Claim
18 words
The flash memory device of claim 15 , wherein the mode of the operation comprises a program mode.
Claim 20
Dependent Claim
31 words
The flash memory device of claim 15 , wherein the electrically isolating means comprises means for disconnecting the predetermined potential from the common source, thereby causing the common source to float.
Claim 21
Independent Claim
76 words
A method of programming a selected flash memory cell in a NOR-type flash memory device architecture, the device having a plurality of flash memory cells organized in a NOR-type array and each of the plurality of flash memory cells having a source terminal coupled together to form a common source, comprising: causing the common source to float during a program mode of operation; and programming the selected flash memory cell while the common source is floating.
Claim 22
Independent Claim
76 words
A method of programming a selected flash memory cell in a NOR-type flash memory device architecture, the device having a plurality of flash memory cells organized in a NOR-type array and each of the plurality of flash memory cells having a source terminal coupled together to form a common source, comprising: causing the common source to float during a program mode of operation; and programming the selected flash memory cell while the common source is floating.
Claim 23
Dependent Claim
45 words
The method of claim 18 , further comprising: determining whether a mode of operation is the program mode, a read mode or an erase mode; and proceeding to the floating of the common source if the operation mode is determined to be the program mode.
Claim 24
Dependent Claim
23 words
The method of claim 18 , wherein causing the common source to float comprises electrically decoupling the common source from a predetermined potential.
Claim 25
Dependent Claim
36 words
The method of claim 20 , wherein electrically decoupling the common source from the predetermined potential comprises turning off a transistor connected between the common source and the predetermined potential during the program mode of operation.
Claim 26
Dependent Claim
55 words
The method of claim 21 , further comprising: generating a control signal based on the determination of the mode of operation; and inputting the control signal to a control terminal of the transistor, wherein the control signal is operable to deactivate the transistor when the mode of operation is determined to be the program mode.
Claim 27
Independent Claim
112 words
A method of programming flash memory cells within a NOR-type flash memory device architecture, wherein a plurality of flash memory cells within the device have a source terminal coupled together to form a common source, comprising: determining an operational mode of the flash memory device; identifying a flash memory cells within the plurality of flash memory cells as a selected cell for programming if the operational mode is determined to be a program mode; activating a bit line associated with the selected cell; floating the common source; activating a word line associated with the selected memory cell with a programming voltage after floating the common source, thereby programming the selected memory cell.
Claim 28
Independent Claim
112 words
A method of programming flash memory cells within a NOR-type flash memory device architecture, wherein a plurality of flash memory cells within the device have a source terminal coupled together to form a common source, comprising: determining an operational mode of the flash memory device; identifying a flash memory cells within the plurality of flash memory cells as a selected cell for programming if the operational mode is determined to be a program mode; activating a bit line associated with the selected cell; floating the common source; activating a word line associated with the selected memory cell with a programming voltage after floating the common source, thereby programming the selected memory cell.
Claim 29
Dependent Claim
44 words
The method of claim 23 , further comprising: removing the programming voltage from the word line associated with the selected memory cell after the selected memory cell has been programmed; coupling the common source to a predetermined potential; and deactivating the activated bit line.
Claim 30
Dependent Claim
42 words
The method of claim 23 , wherein determining the operational mode of the flash memory device comprises: receiving one or more signals indicative of the operational mode; and determining the operational mode based on a state of the one or more signals.
Claim 31
Dependent Claim
23 words
The method of claim 25 , further comprising generating a control signal if the operational mode is determined to be the program mode.
Claim 32
Dependent Claim
21 words
The method of claim 26 , further comprising using the control signal to float the common source during the program mode.
Claim 33
Dependent Claim
33 words
The method of claim 27 , further comprising: placing a transistor between the common source and a predetermined potential; and using the control signal to turn off the transistor during the program mode.
Claim 34
Dependent Claim
28 words
The method of claim 23 , wherein activating the bit line comprises coupling a bit line voltage to the bit line associated with the selected flash memory cell.
Claim 35
Dependent Claim
21 words
The method of claim 23 , wherein floating the common source comprises electrically decoupling the common source from a predetermined potential.
Claim 36
Dependent Claim
23 words
The method of claim 23 , wherein activating the word line comprises coupling the programming voltage thereto for a predetermined period of time.
Claim 37
Dependent Claim
58 words
The method of claim 23 , wherein determining the operational mode and identifying the selected cell in the program mode comprises initiating a program mode control sequence, wherein the activating of the bit line occurs a predetermined period of time before the activating of the word line to ensure that the bit line is sufficiently charged during programming.
Claim 38
Dependent Claim
54 words
The method of claim 32 , wherein the program mode control sequence further dictates that the floating of the common source occurs before the activation of the word line to prevent leakage associated with one or more unselected flash memory cells associated with the activated bit line during programming of the selected memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-26 | 2006-11-25 | 2007-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-26 | 2010-11-25 | 2011-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-26 | 2014-11-25 | 2015-05-27 | $7700.00 | Window Closed / Lapsed |