US6449188B1
Expired / Lapsed
US
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Low column leakage nor flash array-double cell implementation
Assignee: Monterey Research LLC
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Filing: 2001-06-19
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Granted: 2002-09-10
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Expires: 2021-06-19
Abstract
Abstract The present invention relates to a flash memory array architecture, comprising a plurality of bit lines, wherein each of the bit lines comprise a plurality of memory cells associated therewith. The plurality of memory cells are configured as sets of two series-connected memory cells, wherein two sets of such memory cells are coupled together in parallel between a respective bit line and an individually selectable source line. In addition, the flash memory array architecture comprises a plurality of word lines, wherein each of the plurality of memory cells associated with one of the plurality of bits lines is coupled to a respective one of the plurality of word lines. The present invention further comprises a method of reading flash memory cells associated with such an architecture.
Inventors
- 👤 Richard Fastow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:55
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/0483; G11C16/06; G11C16/26
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
98 words
A flash memory array architecture, comprising: a plurality of bit lines, wherein each of the bit lines comprise a plurality of memory cells associated therewith, wherein the plurality of memory cells are configured as sets of two series-connected memory cells, wherein two sets of such memory cells are coupled together in parallel between a respective bit line and an individually selectable source line; and a plurality of word lines, wherein each of the plurality of memory cells associated with one of the plurality of bits lines is coupled to a respective one of the plurality of word lines.
Claim 2
Dependent Claim
98 words
A flash memory array architecture, comprising: a plurality of bit lines, wherein each of the bit lines comprise a plurality of memory cells associated therewith, wherein the plurality of memory cells are configured as sets of two series-connected memory cells, wherein two sets of such memory cells are coupled together in parallel between a respective bit line and an individually selectable source line; and a plurality of word lines, wherein each of the plurality of memory cells associated with one of the plurality of bits lines is coupled to a respective one of the plurality of word lines.
Claim 3
Dependent Claim
95 words
The flash memory array architecture of claim 1 , wherein a first set of series-connected memory cells comprises: a first flash memory cell having a drain terminal coupled to the respective bit line, a gate terminal coupled to one of the plurality of word lines, and a source terminal; and a second flash memory cell having a drain terminal coupled to the source terminal of the first flash memory cell, a gate terminal coupled to a second one of the plurality of word lines, and a source terminal coupled to the individually selectable source line.
Claim 4
Dependent Claim
103 words
The flash memory array architecture of claim 2 , wherein a second set of series-connected memory cells connected in parallel with the first set comprises: a third flash memory cell having a drain terminal coupled to the respective bit line, a gate terminal coupled to a third one of the plurality of word lines, and a source terminal; and a fourth flash memory cell having a drain terminal coupled to the source terminal of the third flash memory cell, a gate terminal coupled to fourth one of the plurality of word lines, and a source terminal coupled to the individually selectable source line.
Claim 5
Dependent Claim
141 words
The flash memory array architecture of claim 1 , further comprising an address control circuit associated with the array of flash memory cells, wherein the address control circuit is operable to generate a plurality of voltages when a flash memory cell is to be read, and further operable to coupled a first voltage to the respective bit line associated with the flash memory cell to be read, couple a read voltage to the word line associated with the cell to be read, couple a pass voltage to the word line of the flash memory cell connected in series with the flash memory cell to be read, couple a second voltage which is less than the first voltage to the word lines of the remaining bit lines and the individually selectable source line associated with the flash memory cell to be read.
Claim 6
Dependent Claim
37 words
The flash memory array architecture of claim 4 , wherein the address control circuit further couples the remaining individually selectable source lines to a high impedance state or allows the remaining individually selectable source lines to float.
Claim 7
Dependent Claim
18 words
The flash memory array architecture of claim 4 , wherein the first voltage comprises a supply voltage value.
Claim 8
Dependent Claim
20 words
The flash memory array architecture of claim 6 , wherein the pass voltage is substantially equal to the first voltage.
Claim 9
Dependent Claim
18 words
The flash memory array architecture of claim 4 , wherein the second voltage comprises a circuit ground potential.
Claim 10
Independent Claim
280 words
A method of reading a flash memory array, wherein the flash memory array comprises a plurality of bit lines, wherein each of the bit lines comprise a plurality of memory cells associated therewith, and wherein the plurality of memory cells are configured as sets of two series-connected memory cells, and wherein two sets of such memory cells are coupled together in parallel between a respective bit line and an individually selectable source line, and wherein the flash memory array further comprises a plurality of word lines, wherein each of the plurality of memory cells associated with one of the plurality of bits lines is coupled to a respective one of the plurality of word lines, comprising the steps of: coupling a bit line associated with a flash memory cell to be read to a first voltage; coupling the individually selectable source line associated with the flash memory cell to be read to a second voltage, wherein the second voltage is less than the first voltage; coupling a word line associated with the flash memory cell to be read to a read voltage; coupling a word line associated with the flash memory cell which is coupled in series with the flash memory cell to be read to a pass voltage; coupling word lines associated with a set of series-connected flash memory cells which are coupled in parallel with a set of series-connected flash memory cells containing the flash memory cell to be read to a third voltage, wherein the third voltage is less than the first voltage; and detecting a current associated with the flash memory cell to be read, wherein the current is indicative of a data value associated therewith.
Claim 11
Independent Claim
280 words
A method of reading a flash memory array, wherein the flash memory array comprises a plurality of bit lines, wherein each of the bit lines comprise a plurality of memory cells associated therewith, and wherein the plurality of memory cells are configured as sets of two series-connected memory cells, and wherein two sets of such memory cells are coupled together in parallel between a respective bit line and an individually selectable source line, and wherein the flash memory array further comprises a plurality of word lines, wherein each of the plurality of memory cells associated with one of the plurality of bits lines is coupled to a respective one of the plurality of word lines, comprising the steps of: coupling a bit line associated with a flash memory cell to be read to a first voltage; coupling the individually selectable source line associated with the flash memory cell to be read to a second voltage, wherein the second voltage is less than the first voltage; coupling a word line associated with the flash memory cell to be read to a read voltage; coupling a word line associated with the flash memory cell which is coupled in series with the flash memory cell to be read to a pass voltage; coupling word lines associated with a set of series-connected flash memory cells which are coupled in parallel with a set of series-connected flash memory cells containing the flash memory cell to be read to a third voltage, wherein the third voltage is less than the first voltage; and detecting a current associated with the flash memory cell to be read, wherein the current is indicative of a data value associated therewith.
Claim 12
Dependent Claim
23 words
The method of claim 9 , wherein the first voltage comprises a voltage value which is approximately equal to a voltage supply value.
Claim 13
Dependent Claim
23 words
The method of claim 9 , wherein the second voltage comprises a voltage value which is approximately equal to a circuit ground potential.
Claim 14
Dependent Claim
20 words
The method of claim 9 , wherein the second voltage and the third voltage are approximately the same voltage value.
Claim 15
Dependent Claim
26 words
The method of claim 12 , wherein the second voltage and third voltage comprise a voltage value which is approximately equal to a circuit ground potential.
Claim 16
Dependent Claim
42 words
The method of claim 9 , wherein the read voltage comprises a voltage value which is greater than a threshold voltage value of an unprogrammed flash memory cell, and is less than a threshold voltage value of a programmed flash memory cell.
Claim 17
Dependent Claim
23 words
The method of claim 9 , wherein the pass voltage comprises a voltage value which is approximately equal to a supply voltage value.
Claim 18
Dependent Claim
49 words
The method of claim 9 , wherein detecting the current comprises: coupling the flash memory cell to be read to a sense amplifier; comparing the detected current to a target value; and determining whether the flash memory cell to be read is programmed or unprogrammed based on the comparison.
Claim 19
Dependent Claim
32 words
The method of claim 16 , wherein comparing the detected current to a target value comprises converting the detected current to a voltage and comparing the voltage to a predetermined voltage value.
Claim 20
Dependent Claim
17 words
The method of claim 9 , further comprising coupling the remaining word lines to the second voltage.
Claim 21
Dependent Claim
28 words
The method of claim 9 , further comprising coupling the bit lines which are not associated with the flash memory cell to be read to the second voltage.
Claim 22
Dependent Claim
39 words
The method of claim 9 , further comprising coupling any individually selectable source lines not associated with the flash memory cell to be read to a high impedance state or allowing the such individually selectable source lines to float.
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