Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge

Abstract

Abstract A process for discharging a floating gate semiconductor device formed in a semiconductor substrate, the device having a first active region, a second active region, a charge holding region, and a channel between the first and second active regions, the channel having a length defined by a distance below the charge holding region between the first and second active regions. The process comprises the steps of: applying a first positive voltage of about 4-8 volts to the first active region; applying a second voltage in the range of about 0.5-3 volts to the second active region; applying a third voltage in the range of minus 8 volts to the charge holding region; and coupling the substrate to ground. The first active region may comprise either a source or a drain region of a MOSFET, and the second active region may comprise a source region or a drain region of a MOSFET. In a further aspect an array of floating gate transistors, each transistor comprising a source, drain, gate and floating gate, each floating gate including an electric charge; and control logic coupled to the transistors, for selectively addressing the transistors is disclosed. In the apparatus, to discharge the floating gates of each transistor in the array: each source is coupled in common to a first voltage; each drain is coupled in common to a second voltage lower than the first voltage; the substrate is coupled to ground; and each floating gate is coupled to a negative voltage.

Inventors

• 👤 Jian Chen
• 👤 James J. Hsu
• 👤 Shengwen Luan
• 👤 Yuan Tang
• 👤 David Kuan-Yu Liu
• 👤 Michael A. Van Buskirk

Bibliographic Details