US5452248A
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Method of operating a nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1992-06-26
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Granted: 1995-09-19
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Expires: 2012-06-26
Abstract
Abstract In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.
Inventors
- 👤 Kiyomi Naruke
- 👤 Tomoko Suzuki
- 👤 Seiji Yamada
- 👤 Etsushi Obi
- 👤 Masamitsu Oshikiri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:46
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; H; H10; H10B; H10B41/00; H10B41/30; G11C16/10; G11C16/14; G11C16/16; H10B41/10; H10B41/20; H10B41/40; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
182 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: discharging electrons held in said electron-holding means by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said electron-holding means in order to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that one of said drain region and said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 2
Independent Claim
182 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: discharging electrons held in said electron-holding means by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said electron-holding means in order to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that one of said drain region and said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 3
Dependent Claim
36 words
The method according to claim 1, wherein said channel region, when said control gate is applied with 0 volts, carries channel current smaller than that flowing when said control gate is applied with a reading voltage.
Claim 4
Dependent Claim
26 words
The method according to claim 2, wherein said avalanche hot carriers are induced by the channel current flowing when said control gate applied with 0 volts.
Claim 5
Dependent Claim
113 words
The method according to claim 3, wherein said electron-holding means comprises a floating gate, and said gate insulator comprises an insulating film, and the electrons held in said electron-holding means are discharged into said one of said source region, said drain region and said substrate by applying a voltage between said control gate and said one of said source region, said drain region and said substrate so that said one of said source, said drain region and said substrate region is at a higher potential, to allow F-N tunnel current to flow through said insulating film between said floating gate and said one of said source region, said drain region and said substrate.
Claim 6
Dependent Claim
138 words
The method according to claim 4, wherein said avalanche hot carriers include avalanche hot electrons and avalanche hot holes, and said floating gate has a balanced potential at which the amount of said avalanche hot electrons injected into said floating gate balances with the amount of said avalanche hot holes injected into said floating gate, and when the potential of said floating gate after the discharge of said electrons into said one of said source region, said drain region and said substrate is more positive than said balanced potential, more of said avalanche hot electrons than said avalanche hot holes are injected into said floating gate, whereas when the potential of said floating gate is more negative than said balanced potential, more of said avalanche hot holes than said avalanche hot electrons are injected into said floating gate.
Claim 7
Dependent Claim
53 words
The method according to claim 5, wherein said electrons are discharged into said one of said source region, said drain region and said substrate so that the potential of said floating gate may be more positive than said balanced potential, to suppress the injection of said avalanche hot holes into said floating gate.
Claim 8
Dependent Claim
55 words
The method according to claim 6, wherein an impurity concentration of said channel region is increased thereby inhibiting a threshold voltage decreasing due to the assistance of the potential of said floating gate when the potential of said floating gate is set at positive value close to said balanced potential after said discharge of electrons.
Claim 9
Independent Claim
241 words
A method of erasing and programming a nonvolatile semiconductor memory device, said nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and one of said source region, said drain region, and said substrate so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential than said drain region, while simultaneously applying a voltage of 0 volts to said control gate; and then injecting electrons into said electron-holding means to program data into said device by applying a voltage between said source region and said drain region so that said drain region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 10
Independent Claim
241 words
A method of erasing and programming a nonvolatile semiconductor memory device, said nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and one of said source region, said drain region, and said substrate so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential than said drain region, while simultaneously applying a voltage of 0 volts to said control gate; and then injecting electrons into said electron-holding means to program data into said device by applying a voltage between said source region and said drain region so that said drain region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 11
Dependent Claim
36 words
The method according to claim 8, wherein said channel region, when said control gate is applied with 0 volts, carries channel current smaller than that flowing when said control gate is applied with the reading voltage.
Claim 12
Dependent Claim
27 words
The method according to claim 9, wherein said avalanche hot carriers are induced by the channel current flowing when said control gate is applied with 0 volts.
Claim 13
Dependent Claim
114 words
The method according to claim 10, wherein said electron-holding means comprises a floating gate, and said gate insulator comprises an insulating film, and the electrons held in said electron-holding means are discharged into said one of said source region, said drain region and said substrate by applying a voltage between said control gate and said one of said source region, said drain region and said substrate so that said one of said source region, said drain region and said substrate region is at a higher potential, to allow F-N tunnel current to flow through said insulating film between said floating gate and said one of said source region, said drain region and said substrate.
Claim 14
Dependent Claim
138 words
The method according to claim 11, wherein said avalanche hot carriers include avalanche hot electrons and avalanche hot holes, and said floating gate has a balanced potential at which the amount of said avalanche hot electrons injected into said floating gate balances with the amount of said avalanche hot holes injected into said floating gate, and when the potential of said floating gate after the discharge of said electrons into said one of said source region, said drain region and said substrate is more positive than said balanced potential, more of said avalanche hot electrons than said avalanche hot holes are injected into said floating gate, whereas when the potential of said floating gate is more negative than said balanced potential, more of said avalanche hot holes than said avalanche hot electrons are injected into said floating gate.
Claim 15
Dependent Claim
53 words
The method according to claim 12, wherein said electrons are discharged into said one of said source region, said drain region and said substrate so that the potential of said floating gate may be more positive than said balanced potential, to suppress the injection of said avalanche hot holes into said floating gate.
Claim 16
Dependent Claim
54 words
The method according to claim 13, wherein an impurity concentration of said channel region is increased, thereby inhibiting a threshold voltage decreasing due to the assistance the potential of said floating gate when the potential of said floating gate is set at positive value closed to said balanced potential after said discharge of electrons.
Claim 17
Dependent Claim
21 words
The method according to claim 8, wherein said injected electrons for programming the data for said device are channel hot electrons.
Claim 18
Independent Claim
224 words
A method of erasing and programming a nonvolatile semiconductor memory device, said nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: injecting avalanche hot carriers into said electron-holding means by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate; and then discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and one of said source region, said drain region, and said substrate so that said one of said source region, said drain region, and said substrate has a potential greater than a potential of said control gate; and then injecting hot channel electrons into said electron-holding means to program the device by applying a voltage between said source region and said drain region so that said drain region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 19
Independent Claim
224 words
A method of erasing and programming a nonvolatile semiconductor memory device, said nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: injecting avalanche hot carriers into said electron-holding means by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate; and then discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and one of said source region, said drain region, and said substrate so that said one of said source region, said drain region, and said substrate has a potential greater than a potential of said control gate; and then injecting hot channel electrons into said electron-holding means to program the device by applying a voltage between said source region and said drain region so that said drain region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 20
Dependent Claim
36 words
The method according to claim 16, wherein said channel region, when 0 volts is applied to said control gate, carries channel current smaller than that flowing when said control gate is applied with the reading voltage.
Claim 21
Dependent Claim
17 words
The method according to claim 17, wherein said avalanche hot carriers are induced by said channel current.
Claim 22
Dependent Claim
113 words
The method according to claim 18, wherein said electron-holding means comprises a floating gate, and said gate insulator comprises an insulating film, and the electrons held in said electron-holding means are discharged into said one of said source region, said drain region and said substrate by applying a voltage between said control gate and said one of said source region, said drain region and said substrate so that said one of said source, said drain region and said substrate region is at a higher potential, to allow F-N tunnel current to flow through said insulating film between said floating gate and said one of said source region, said drain region and said substrate.
Claim 23
Dependent Claim
138 words
The method according to claim 19, wherein said avalanche hot carriers include avalanche hot electrons and avalanche hot holes, and said floating gate has a balanced potential at which the amount of said avalanche hot electrons injected into said floating gate balances with the amount of said avalanche hot holes injected into said floating gate, and when the potential of said floating gate after the discharge of said electrons into said one of said source region, said drain region and said substrate is more positive than said balanced potential, more of said avalanche hot electrons than said avalanche hot holes are injected into said floating gate, whereas when the potential of said floating gate is more negative than said balanced potential, more of said avalanche hot holes than said avalanche hot electrons are injected into said floating gate.
Claim 24
Dependent Claim
53 words
The method according to claim 20, wherein said electrons are discharged into said one of said source region, said drain region and substrate so that the potential of said floating gate is more positive than said balanced potential in order to suppress the injection of said avalanche hot holes into said floating gate.
Claim 25
Dependent Claim
55 words
The method according to claim 21, wherein an impurity concentration of said channel region is increased, thereby inhibiting a threshold voltage decreasing due to the assistance of the potential of said floating gate when the potential of said floating gate is set at positive value close to said balanced potential after said discharge of electrons.
Claim 26
Dependent Claim
233 words
An electrically erasable/programmable nonvolatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array comprising a plurality of memory cells formed on said semiconductor substrate, each memory cell comprising: source and drain regions formed on said semiconductor substrate which define a channel region therebetween; an electron-holding means; and a control gate insulatively spaced from said channel region; a tunnel erase control circuit for controlling the respective potentials of said substrate and of said control gate, said source region, and said drain region each cell within said memory cell array to discharge electrons stored in said electron-holding means by Fowler-Nordheim tunnel current; an avalanche hot carrier injection control circuit for controlling the respective potentials of said substrate and of said control gate, said source region, and said drain region of each cell within said memory cell array to balance the potential of said electron-holding means such that the amount of avalanche hot electrons injected into said electron-holding means balances with the amount of avalanche hot holes injected into said electron-holding means, said avalanche hot carrier injection control circuit applying a voltage of 0 volts to said control gate and a voltage higher than the voltage of said control gate to said source region to inject avalanche hot electrons into said electron-holding means; and data erasure control means for sequentially activating/deactivating said tunnel erase control circuit and said avalanche hot carrier injection control circuit.
Claim 27
Dependent Claim
233 words
An electrically erasable/programmable nonvolatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array comprising a plurality of memory cells formed on said semiconductor substrate, each memory cell comprising: source and drain regions formed on said semiconductor substrate which define a channel region therebetween; an electron-holding means; and a control gate insulatively spaced from said channel region; a tunnel erase control circuit for controlling the respective potentials of said substrate and of said control gate, said source region, and said drain region each cell within said memory cell array to discharge electrons stored in said electron-holding means by Fowler-Nordheim tunnel current; an avalanche hot carrier injection control circuit for controlling the respective potentials of said substrate and of said control gate, said source region, and said drain region of each cell within said memory cell array to balance the potential of said electron-holding means such that the amount of avalanche hot electrons injected into said electron-holding means balances with the amount of avalanche hot holes injected into said electron-holding means, said avalanche hot carrier injection control circuit applying a voltage of 0 volts to said control gate and a voltage higher than the voltage of said control gate to said source region to inject avalanche hot electrons into said electron-holding means; and data erasure control means for sequentially activating/deactivating said tunnel erase control circuit and said avalanche hot carrier injection control circuit.
Claim 28
Dependent Claim
169 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween; a gate insulator provided on said channel region; an electron-holding means provided on said gate insulator; a control gate insulatively spaced from said electron-holding means; means for discharging electrons held in said electron-holding means by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and means for injecting avalanche hot carriers into said electron-holding means in order to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 29
Dependent Claim
169 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween; a gate insulator provided on said channel region; an electron-holding means provided on said gate insulator; a control gate insulatively spaced from said electron-holding means; means for discharging electrons held in said electron-holding means by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and means for injecting avalanche hot carriers into said electron-holding means in order to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 30
Dependent Claim
222 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween; a gate insulator provided on said channel region; an electron-holding means provided on said gate insulator; a control gate insulatively spaced from said electron-holding means; means for discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and one of said source region, said drain region, and said substrate so that said one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; means for injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate; and means for injecting electrons into said electron-holding means to program data into said device by applying a voltage between said source region and said drain region so that said drain region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 31
Dependent Claim
222 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween; a gate insulator provided on said channel region; an electron-holding means provided on said gate insulator; a control gate insulatively spaced from said electron-holding means; means for discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and one of said source region, said drain region, and said substrate so that said one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; means for injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate; and means for injecting electrons into said electron-holding means to program data into said device by applying a voltage between said source region and said drain region so that said drain region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 32
Independent Claim
158 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, carrier-holding means provided on said gate insulator, and a control gate insulatively spaced from said carrier-holding means, said method comprising the steps of: discharging carriers held in said carder-holding means by applying a voltage between said control gate and one of said source region, said drain region and said substrate, to generate Fowler-Nordheim tunnel current; and injecting avalanche hot carriers into said carrier-holding means, in order to converge the potential of said carrier-holding means to a predetermined value, by applying a voltage between said source and drain region so that one of said drain region and said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 33
Independent Claim
158 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, carrier-holding means provided on said gate insulator, and a control gate insulatively spaced from said carrier-holding means, said method comprising the steps of: discharging carriers held in said carder-holding means by applying a voltage between said control gate and one of said source region, said drain region and said substrate, to generate Fowler-Nordheim tunnel current; and injecting avalanche hot carriers into said carrier-holding means, in order to converge the potential of said carrier-holding means to a predetermined value, by applying a voltage between said source and drain region so that one of said drain region and said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 34
Dependent Claim
39 words
The method according to claim 26, wherein said data is erased from said memory device in said discharging step, and the threshold value of said memory device whose data is erased tends to converge to a particular threshold value.
Claim 35
Dependent Claim
17 words
The method according to claim 27, wherein said avalanche hot carriers are induced by a channel current.
Claim 36
Independent Claim
184 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having a source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, a floating gate provided on said gate insulator, and a control gate insulatively spaced from said floating gate, said method comprising the steps of: discharging electrons held in said floating gate by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said floating gate in order to converge the potential of said floating gate to a predetermined value by applying a voltage between said source region and said drain region so that one of said drain region and said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 37
Independent Claim
184 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having a source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, a floating gate provided on said gate insulator, and a control gate insulatively spaced from said floating gate, said method comprising the steps of: discharging electrons held in said floating gate by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said floating gate in order to converge the potential of said floating gate to a predetermined value by applying a voltage between said source region and said drain region so that one of said drain region and said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 38
Independent Claim
181 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, a floating gate provided on said gate insulator, and a control gate insulatively spaced from said floating gate, said method comprising the steps of: discharging electrons held in said floating gate by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said floating gate from said source region in order to converge the potential of said floating gate to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 39
Independent Claim
181 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having source and drain regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, a floating gate provided on said gate insulator, and a control gate insulatively spaced from said floating gate, said method comprising the steps of: discharging electrons held in said floating gate by applying a voltage between said control gate and one of said source region, said drain region, and said substrate, so that at least one of said source region, said drain region, and said substrate has a potential greater than the potential of said control gate; and then injecting avalanche hot carriers into said floating gate from said source region in order to converge the potential of said floating gate to a predetermined value by applying a voltage between said source region and said drain region so that said source region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate.
Claim 40
Dependent Claim
234 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having first and second regions of a second conductivity type which define a channel region therebetween; a gate insulator provided on said channel region; an electron-holding means provided on said gate insulator; a control gate insulatively spaced from said electron-holding means; means for discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and said first region, said first region having a potential higher than the potential of said control gate, the electrons held in said electron-holding means being discharged to said first region; means for injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said first region and said second region so that said first region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate, said avalanche hot carriers being injected from said first region to said electron-holding means; and means for injecting electrons from said second region into said electron-holding means to program data into said device by applying a voltage between said first region and said second region so that said second region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 41
Dependent Claim
234 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having first and second regions of a second conductivity type which define a channel region therebetween; a gate insulator provided on said channel region; an electron-holding means provided on said gate insulator; a control gate insulatively spaced from said electron-holding means; means for discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and said first region, said first region having a potential higher than the potential of said control gate, the electrons held in said electron-holding means being discharged to said first region; means for injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said first region and said second region so that said first region is at a higher potential, while simultaneously applying a voltage of 0 volts to said control gate, said avalanche hot carriers being injected from said first region to said electron-holding means; and means for injecting electrons from said second region into said electron-holding means to program data into said device by applying a voltage between said first region and said second region so that said second region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 42
Independent Claim
254 words
A method of erasing and programming a nonvolatile semiconductor memory device, said nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having first and second regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and said first region so that said first region has a potential greater than the potential of said control gate, the electrons held in said electron-holding means being discharged to said first region; and then injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said first region and said second region so that said first region is at a higher potential than said drain region, while simultaneously applying a voltage of 0 volts to said control gate, said avalanche hot carriers being injected from said first region to said electron-holding means; and then injecting electrons from said second region into said electron-holding means to program data into said device by applying a voltage between said first region and said second region so that said second region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 43
Independent Claim
254 words
A method of erasing and programming a nonvolatile semiconductor memory device, said nonvolatile semiconductor memory device including a semiconductor substrate of a first conductivity type having first and second regions of a second conductivity type which define a channel region therebetween, a gate insulator provided on said channel region, electron-holding means provided on said gate insulator, and a control gate insulatively spaced from said electron-holding means, said method comprising the steps of: discharging electrons held in said electron-holding means to erase data from said device by applying a voltage between said control gate and said first region so that said first region has a potential greater than the potential of said control gate, the electrons held in said electron-holding means being discharged to said first region; and then injecting avalanche hot carriers into said electron-holding means to converge the potential of said electron-holding means to a predetermined value by applying a voltage between said first region and said second region so that said first region is at a higher potential than said drain region, while simultaneously applying a voltage of 0 volts to said control gate, said avalanche hot carriers being injected from said first region to said electron-holding means; and then injecting electrons from said second region into said electron-holding means to program data into said device by applying a voltage between said first region and said second region so that said second region is at a higher potential, while simultaneously applying a voltage higher than a reading voltage to said control gate.
Claim 44
Dependent Claim
21 words
The method according to claim 16, wherein said injected electrons for programming the data for said device are channel hot electrons.
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