Single transistor flash EPROM cell and method of operation

Claim 1

A flash EPROM memory cell array comprising: a plurality of flash EPROM memory cells arranged as a matrix of rows and columns of said memory cells, each memory cell including a memory cell transistor having source and drain regions formed in a silicon substrate in spaced-apart relationship to define a channel region therebetween, a floating gate formed above the channel region to overlap the source and drain regions and separated therefrom by a layer of tunnel dielectric material, and a control gate formed above the floating gate and separated therefrom by a layer of inter-gate dielectric material; for each row of flash memory cells in said matrix, a corresponding bit line connected to the drain region of each memory cell transistor in said row; for each column of flash memory cells in said matrix, a corresponding word line connected to the control gate of each memory cell transistor in said column; and bias circuitry for applying read bias voltages to the array for reading data from a selected flash memory cell in said matrix, wherein said read bias circuitry includes means for applying a first control gate voltage to the word line connected to the control gate of said selected flash memory cell and a second control gate voltage to the word lines of the matrix excluding the word line associated with the selected flash memory cell, the first control gate voltage being positive and higher than the highest erased threshold voltage from the erased flash memory cell threshold voltage distribution and less than the lowest programmed threshold voltage from the programmed flash memory cell threshold distribution such that programmed flash memory cells connected to the selected wordline are shut off with insignificant drain current conduction, the second control gate voltage being less than the lowest erased threshold voltage such that erased cells connected to deselected wordlines are shut off with insignificant drain current conduction when said second control gate voltage is applied to the gates of said erased cells, even if said erased cells are overerased to negative threshold voltages.