US5949718A
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Method and system for selected source during read and programming of flash memory
Assignee: University of Pennsylvania
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Filing: 1997-12-17
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Granted: 1999-09-07
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Expires: 2017-12-17
Abstract
Abstract A system and method for providing a flash memory is disclosed. The flash memory includes a plurality of memory cells. Each memory cell includes a source and a gate. The method and system include providing a plurality of word lines and a plurality of select devices. Each word line is coupled with the gate of each memory cell of a portion of the plurality of memory cells. Each word line provides a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells. The plurality of select devices correspond with the plurality of word lines. Each select device is coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line. Each select device couples the source of each memory cell of the portion of the plurality of memory cell with a specific potential during the read of the memory cell. The method and system reduce the number of memory cells coupled in parallel with the memory cell during the read.
Inventors
- 👤 Mark Randolph
- 👤 Collin Bill
- 👤 Michael Van Buskirk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:03
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
179 words
A system for providing a flash memory including a plurality of memory cells, each memory cell including a source and a gate, the system comprising: a plurality of word lines, each word line of the plurality of word lines coupled with the gate of each memory cell of a portion of the plurality of memory cells, each word line for providing a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells; and a plurality of select devices corresponding to the plurality of word lines, each select device of the plurality of select devices coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line, each select device of the plurality of select devices coupling the source of each memory cell of the portion of the plurality of memory cells with a specific potential during the read of the memory cell of the portion of the plurality of memory cells.
Claim 2
Independent Claim
179 words
A system for providing a flash memory including a plurality of memory cells, each memory cell including a source and a gate, the system comprising: a plurality of word lines, each word line of the plurality of word lines coupled with the gate of each memory cell of a portion of the plurality of memory cells, each word line for providing a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells; and a plurality of select devices corresponding to the plurality of word lines, each select device of the plurality of select devices coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line, each select device of the plurality of select devices coupling the source of each memory cell of the portion of the plurality of memory cells with a specific potential during the read of the memory cell of the portion of the plurality of memory cells.
Claim 3
Dependent Claim
44 words
The system of claim 1 wherein each select device of the plurality of select devices is further coupled with the corresponding word line, each of the plurality of select devices being turned on by application of the specific voltage on the corresponding word line.
Claim 4
Dependent Claim
11 words
The system of claim 2 wherein the specific potential is ground.
Claim 5
Dependent Claim
25 words
The system of claim 3 wherein each select device of the plurality of select devices further includes a gate coupled to the corresponding word line.
Claim 6
Dependent Claim
46 words
The system of claim 4 further comprising a plurality of erase elements coupled with the sources of the portion of the plurality of memory cells, the plurality of erase elements providing an erase voltage to the sources of the portion of the plurality of memory cells.
Claim 7
Dependent Claim
17 words
The system of claim 5 wherein the plurality of select devices further comprise a plurality of transistors.
Claim 8
Dependent Claim
19 words
The system of claim 6 wherein the plurality of memory cells further comprise a plurality of floating gate transistors.
Claim 9
Dependent Claim
48 words
The system of claim 7 wherein each of the plurality of memory cells further includes a drain, the system further comprising: a plurality of bit lines, each of the plurality of bit lines being coupled with the drains of a second portion of the plurality of memory cells.
Claim 10
Dependent Claim
18 words
The system of claim 8 wherein the plurality of bit lines further allow erasure of a single memory.
Claim 11
Independent Claim
181 words
A method for providing a flash memory including a plurality of memory cells, each memory cell including a source and a gate, the method comprising the steps of: providing a plurality of word lines, each word line of the plurality of word lines coupled with the gate of each memory cell of a portion of the plurality of memory cells, each word line for providing a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells; and providing a plurality of select devices corresponding with the plurality of word lines, each select device of the plurality of select devices coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line, each select device of the plurality of select devices coupling the source of each memory cell of the portion of the plurality of memory cell with a specific potential during the read of the memory cell of the plurality of memory cells.
Claim 12
Independent Claim
181 words
A method for providing a flash memory including a plurality of memory cells, each memory cell including a source and a gate, the method comprising the steps of: providing a plurality of word lines, each word line of the plurality of word lines coupled with the gate of each memory cell of a portion of the plurality of memory cells, each word line for providing a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells; and providing a plurality of select devices corresponding with the plurality of word lines, each select device of the plurality of select devices coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line, each select device of the plurality of select devices coupling the source of each memory cell of the portion of the plurality of memory cell with a specific potential during the read of the memory cell of the plurality of memory cells.
Claim 13
Dependent Claim
29 words
The method of claim 10 wherein each select device is further coupled with the corresponding word line, the select device being turned on by application of the specific voltage.
Claim 14
Dependent Claim
11 words
The method of claim 11 wherein the specific potential is ground.
Claim 15
Dependent Claim
19 words
The method of claim 12 wherein each select device further includes a gate coupled to the corresponding word line.
Claim 16
Dependent Claim
50 words
The method of claim 13 further comprising the step of: providing a plurality of erase elements coupled with the sources of the portion of the plurality of memory cells, the plurality of erase elements providing an erase voltage to the sources of the portion of the plurality of memory cells.
Claim 17
Dependent Claim
17 words
The method of claim 14 wherein the plurality of select devices further comprise a plurality of transistors.
Claim 18
Dependent Claim
19 words
The method of claim 15 wherein the plurality of memory cells further comprise a plurality of floating gate transistors.
Claim 19
Dependent Claim
52 words
The method of claim 16 wherein each of the plurality of memory cells further includes a drain, the method further comprising the step of: providing a plurality of bit lines, each of the plurality of bit lines being coupled with the drains of a second portion of the plurality of memory cells.
Claim 20
Dependent Claim
18 words
The method of claim 17 wherein the plurality of bit lines further allow erasure of a single memory.
Claim 21
Independent Claim
166 words
A method for reading a flash memory including a plurality of memory cells, a plurality of word lines, and a plurality of select devices corresponding to the plurality of word lines, each memory cell including a source and a gate, each word line of the plurality of word lines coupled with the gates of a portion of the plurality of memory cells, each of the select devices being coupled with the sources of the portion of the plurality of memory cells coupled with the corresponding word line, the method comprising the steps of: providing a specific voltage on a word line of the plurality of word lines for reading a memory cell of the portion of the plurality of memory cells coupled with the word line; and providing a potential to the sources of the portion of the plurality of memory cells memory cells coupled with the corresponding word line by turning on the select device of the plurality of devices corresponding to the word line.
Claim 22
Independent Claim
166 words
A method for reading a flash memory including a plurality of memory cells, a plurality of word lines, and a plurality of select devices corresponding to the plurality of word lines, each memory cell including a source and a gate, each word line of the plurality of word lines coupled with the gates of a portion of the plurality of memory cells, each of the select devices being coupled with the sources of the portion of the plurality of memory cells coupled with the corresponding word line, the method comprising the steps of: providing a specific voltage on a word line of the plurality of word lines for reading a memory cell of the portion of the plurality of memory cells coupled with the word line; and providing a potential to the sources of the portion of the plurality of memory cells memory cells coupled with the corresponding word line by turning on the select device of the plurality of devices corresponding to the word line.
Claim 23
Dependent Claim
68 words
The method of claim 19 wherein the each of the plurality of select devices further includes a gate coupled with the corresponding word line of the plurality of word lines, the step of providing the potential to the sources further comprising the step of: providing the specific voltage on the word line corresponding to the select device, wherein the select device is turned on by the specific voltage.
Claim 24
Dependent Claim
10 words
The method of claim 20 wherein the potential is ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |