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US5120671A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for self aligning a source region with a field oxide region and a polysilicon gate

Assignee: Intel Corp
•
Filing: 1990-11-29
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Granted: 1992-06-09
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Expires: 2010-11-29
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Abstract

Abstract A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

Inventors

  • 👤 Daniel N. Tang
  • 👤 Wen-Juei Lu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 21:40
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/10; H10B41/30; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 169 words
In a semiconductor device having a silicon substrate, a method of forming source regions in said silicon substrate said source regions self-aligned with polysilicon regions and field oxide regions, said method comprising: a) forming continuous substantially parallel field oxide regions on said silicon substrate; b) forming continuous substantially parallel gate oxide regions on said silicon substrate between said field oxide regions; c) forming continuous substantially parallel polysilicon regions on said continuous substantially parallel field oxide regions and on said continuous substantially parallel gate oxide regions, said continuous substantially parallel polysilicon regions being substantially perpendicular to said continuous substantially parallel field oxide regions and to said continuous substantially parallel gate oxide regions; d) etching said continuous substantially parallel field oxide regions and said continuous substantially parallel gate oxide regions exposed between said continuous substantially parallel polysilicon regions using a high selectivity oxide etch; e) forming said self-aligned source regions in select portions of said silicon substrate exposed between said continuous substantially parallel polysilicon regions and said etched field oxide regions.
Claim 2
Dependent Claim 169 words
In a semiconductor device having a silicon substrate, a method of forming source regions in said silicon substrate said source regions self-aligned with polysilicon regions and field oxide regions, said method comprising: a) forming continuous substantially parallel field oxide regions on said silicon substrate; b) forming continuous substantially parallel gate oxide regions on said silicon substrate between said field oxide regions; c) forming continuous substantially parallel polysilicon regions on said continuous substantially parallel field oxide regions and on said continuous substantially parallel gate oxide regions, said continuous substantially parallel polysilicon regions being substantially perpendicular to said continuous substantially parallel field oxide regions and to said continuous substantially parallel gate oxide regions; d) etching said continuous substantially parallel field oxide regions and said continuous substantially parallel gate oxide regions exposed between said continuous substantially parallel polysilicon regions using a high selectivity oxide etch; e) forming said self-aligned source regions in select portions of said silicon substrate exposed between said continuous substantially parallel polysilicon regions and said etched field oxide regions.
Claim 3
Dependent Claim 16 words
The method of claim 1 wherein in step (a) said field oxide regions are thermally grown.
Claim 4
Dependent Claim 16 words
The method of claim 2 wherein in step (b) said gate oxide regions are thermally grown.
Claim 5
Dependent Claim 28 words
The method of claim 3 wherein in step (c) said continuous substantially parallel polysilicon regions are formed by chemically depositing polysilicon and etching select portions of said polysilicon.
Claim 6
Dependent Claim 17 words
The method of claim 4 wherein in step (f) said source regions are formed using ion implantation.
Claim 7
Dependent Claim 57 words
The method of claim 5 wherein in step (f) said select portions of said silicon substrate exposed between said continuous substantially parallel polysilicon regions and said etched field oxide regions are selected by forming a mask over non-select portions of said silicon substrate exposed between said continuous substantially parallel polysilicon regions and said etched field oxide regions.
Claim 8
Dependent Claim 28 words
The method of claim 6 wherein said etching process in step (e) is achieved with a plasma etch process using a radio frequency (RF) power of 1200 watts.
Claim 9
Dependent Claim 26 words
The method of claim 7 wherein said etching process in step (e) is achieved with a plasma etch process having an atmospheric pressure of 50 mTorr.
Claim 10
Dependent Claim 41 words
The method of claim 8 wherein said etching process in step (e) is achieved with a plasma etch process having a gas mixture and flow rate of 75 standard cubic centimeters per minute (SCCM) of CHF3 to 5 SCCMs of O2.
Claim 11
Dependent Claim 17 words
The method of claim 9 wherein said self-aligned source regions are source regions of an EPROM device.
Claim 12
Dependent Claim 14 words
The method of claim 10 wherein said EPROM device is a Flash EPROM device.
Claim 13
Dependent Claim 28 words
The method of claim 1 wherein said etching process in step (e) is achieved with a plasma etch process using a radio frequency (RF) power of 1200 watts.
Claim 14
Dependent Claim 26 words
The method of claim 12 wherein said etching process in step (e) is achieved with a plasma etch process having an atmospheric pressure of 50 mTorr.
Claim 15
Dependent Claim 41 words
The method of claim 13 wherein said etching process in step (e) is achieved with a plasma etch process having a gas mixture and flow rate of 75 standard cubic centimeters per minute (SCCM) of CHF3 to 5 SCCMs of O2.
Claim 16
Dependent Claim 17 words
The method of claim 14 wherein said self-aligned source regions are source regions of an EPROM device.
Claim 17
Dependent Claim 18 words
The method of claim 14 wherein said self-aligned source regions are source regions of a Flash EPROM device.

References Cited (Backward Citations)

US4620361A Cited
US4814286A Cited
US4861730A Cited
JPH021946A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-06-09 1995-12-09 1996-06-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-06-09 1999-12-09 2000-06-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-06-09 2003-12-09 2004-06-09 $7700.00 Window Closed / Lapsed

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