Process for making a high density split gate nonvolatile memory cell

Claim 1

A process for making a high density split gate EEPROM cell having source and drain regions spaced by a channel, comprising the steps of: providing a semiconductor body; implanting a P-type impurity in said body; growing a thin oxide layer over said body; depositing and defining a first layer of polysilicon over said thin oxide layer; growing a second gate oxide layer over said first layer of polysilicon and a portion of said body; depositing a second layer of polysilicon over said second gate oxide layer; masking with a first mask and etching said second layer of polysilicon to define a control gate having a first edge positioned above said first layer of polysilicon and a second edge positioned on said second gate oxide above said body; providing a second mask covering the area of said body below which the source region will be formed and covering at least a portion of said first mask such that the surface of said body where said source region will be formed will be protected during an etching process; etching said first layer of polysilicon to define a floating gate with one edge self-aligned with said first edge of said control gate; implanting N-type impurities in said drain region which is self-aligned to said floating gate and said control gate to form an N-type conductivity region; removing said first and second mask; and implanting N-type impurities in said source region which is self-aligned to said control gate and into the drain region.