Semiconductor non-volatile memory device and manufacture therefor

Abstract

Abstract PURPOSE:To increase integration and to reduce erase/write voltage by a method wherein a control gate and a floating gate are extended on a selecting Tr and a thin film section shallower than the diffusion depth at a D region is provided at the end section of a gate insulating film. CONSTITUTION:A selecting gate 20, a first gate oxide film 19, and an N<+> type D region 12 are formed on a P type substrate 1 and a selecting transistor is formed at an S region 13, and the region 13 also consists of an S region 14, a second gate oxide film 17, a floating gate 15, and a control gate 16 at the D region of a memory transistor to unitedly form a memory Tr and a selecting Tr. The floating gate 15 and the control gate 16 extend on the selecting gate 20 and the second gate insulating film 17 becomes a thin film section 18 with 200Angstrom or below around the D region 13 to form a thickness shallower than the diffusion depth of the D region. In this way, erase/write voltage can be reduced without losing integration.

Inventors

• 👤 Shinpei Tsuchiya
• 👤 Takashi Ito

Bibliographic Details