US20070178643A1 — Memory utilizing oxide-conductor nanolaminates

Claim 1

Independent Claim 79 words

1 . A method for forming a floating gate transistor, comprising: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; and forming a control gate opposing the floating gate and separated therefrom by a second gate oxide.

Claim 2

Dependent Claim 79 words

1 . A method for forming a floating gate transistor, comprising: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; and forming a control gate opposing the floating gate and separated therefrom by a second gate oxide.

Claim 3

Dependent Claim 21 words

2 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Tantalum Nitride (TaN).

Claim 4

Dependent Claim 21 words

3 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Titanium Nitride (TiN).

Claim 5

Dependent Claim 21 words

4 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Tungsten Nitride (WN).

Claim 6

Dependent Claim 21 words

5 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Niobium Nitride (NbN).

Claim 7

Dependent Claim 21 words

6 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Molybdenum Nitride (MoN).

Claim 8

Dependent Claim 20 words

7 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Zinc-Oxide-Silicon (ZnOS).

Claim 9

Dependent Claim 20 words

8 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Tungsten (W).

Claim 10

Dependent Claim 20 words

9 . The method of claim 1 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Nickel (Ni).

Claim 11

Dependent Claim 331 words

10 . A method for forming a multistate memory array, comprising: forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate in the trenches along rows of pillars and separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a multistate cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench, and wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; forming a number of bit lines coupled to the second source/drain region of each floating gate transistor along rows of the memory array; forming a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each floating gate transistor in column adjacent pillars couples to the sourceline in a shared trench such that a multistate cell floating gate transistor and a reference cell floating gate transistor share a common sourceline; and wherein the number of vertical pillars can be programmed to have a charge trapped in the floating gate by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a control gate by a wordline address.

Claim 12

Dependent Claim 331 words

10 . A method for forming a multistate memory array, comprising: forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate in the trenches along rows of pillars and separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a multistate cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench, and wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; forming a number of bit lines coupled to the second source/drain region of each floating gate transistor along rows of the memory array; forming a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each floating gate transistor in column adjacent pillars couples to the sourceline in a shared trench such that a multistate cell floating gate transistor and a reference cell floating gate transistor share a common sourceline; and wherein the number of vertical pillars can be programmed to have a charge trapped in the floating gate by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a control gate by a wordline address.

Claim 13

Dependent Claim 37 words

11 . The method of claim 10 , wherein forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trench.

Claim 14

Dependent Claim 21 words

12 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Tantalum Nitride (TaN).

Claim 15

Dependent Claim 21 words

13 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Titanium Nitride (TiN).

Claim 16

Dependent Claim 21 words

14 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Tungsten Nitride (WN).

Claim 17

Dependent Claim 21 words

15 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Niobium Nitride (NbN).

Claim 18

Dependent Claim 21 words

16 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Molybdenum Nitride (MoN).

Claim 19

Dependent Claim 20 words

17 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Zinc-Oxide-Silicon (ZnOS).

Claim 20

Dependent Claim 20 words

18 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Tungsten (W).

Claim 21

Dependent Claim 20 words

19 . The method of claim 10 , wherein forming oxide-conductor nanolaminate layers includes forming a layer of Nickel (Ni).

Claim 22

Dependent Claim 91 words

20 . A method for forming a memory array, comprising: forming a plurality of memory cells, wherein forming at least one cell includes: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; and forming a control gate opposing the floating gate and separated therefrom by a second gate oxide.

Claim 23

Dependent Claim 91 words

20 . A method for forming a memory array, comprising: forming a plurality of memory cells, wherein forming at least one cell includes: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; and forming a control gate opposing the floating gate and separated therefrom by a second gate oxide.

Claim 24

Dependent Claim 37 words

21 . The method of claim 20 , further including forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the memory cell.

Claim 25

Dependent Claim 22 words

22 . The method of claim 20 , further including forming reading circuitry to read the memory cell in a forward direction.

Claim 26

Dependent Claim 29 words

23 . The method of claim 20 , wherein forming programming circuitry includes forming circuitry to apply a grounding potential to the first source/drain of the floating gate transistor.

Claim 27

Dependent Claim 25 words

24 . The method of claim 20 , wherein forming programming circuitry includes forming circuitry to apply a VDD potential to the second source/drain region.

Claim 28

Dependent Claim 117 words

25 . A method for forming an electronic system, comprising: forming a memory array, wherein forming at least one memory cell in the array includes: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; forming a control gate opposing the floating gate and separated therefrom by a second gate oxide; forming a number of sense amplifiers to detect a signal from memory cells in the memory array; and coupling the memory array to a processor.

Claim 29

Dependent Claim 117 words

25 . A method for forming an electronic system, comprising: forming a memory array, wherein forming at least one memory cell in the array includes: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer; forming a control gate opposing the floating gate and separated therefrom by a second gate oxide; forming a number of sense amplifiers to detect a signal from memory cells in the memory array; and coupling the memory array to a processor.

Claim 30

Dependent Claim 37 words

26 . The method of claim 25 , further including forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the memory cell.

Claim 31

Dependent Claim 22 words

27 . The method of claim 25 , further including forming reading circuitry to read the memory cell in a forward direction.

Memory utilizing oxide-conductor nanolaminates

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