US6381168B2
Expired / Lapsed
US
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Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
Assignee: Micron Technology Inc
•
Filing: 2000-02-04
•
Granted: 2002-04-30
•
Expires: 2020-02-04
Abstract
Abstract A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar junction transistor is described as coupled to a body of the n-channel access transistor. During operation the n-channel field effect transistor is used for writing data to a memory cell, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:54
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/405; H; H10; H10B; H10B12/00; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10B12/30; H10B12/39; H10B12/395
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
69 words
A method of accessing a memory cell, the method comprising: activating a field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell; and activating a bipolar junction transistor coupled between the trench plate trench capacitor of the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 2
Independent Claim
69 words
A method of accessing a memory cell, the method comprising: activating a field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell; and activating a bipolar junction transistor coupled between the trench plate trench capacitor of the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
Claim 4
Dependent Claim
21 words
The method of claim 2 wherein a body of the n-channel transistor is coupled to a base of the NPN transistor.
Claim 5
Dependent Claim
20 words
The method of claim 3 wherein a gate voltage of the field effect transistor varies between zero and three volts.
Claim 6
Independent Claim
21 words
The method of claim wherein 3 a base voltage of the NPN access transistor varies between 0.7 and approximately 1.4 volts.
Claim 7
Dependent Claim
24 words
The method of claim 3 wherein the field effect transistor and the bipolar junction access transistor are fabricated in a common vertical pillar structure.
Claim 8
Dependent Claim
67 words
The method of claim 6 wherein the common vertical pillar structure comprises: a first layer of n-type semiconductor material; a p-type semiconductor material fabricated on top of the first layer of n-type semiconductor material; a gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; and a second layer of n-type semiconductor material fabricated outwardly from the p-type semiconductor material.
Claim 9
Dependent Claim
26 words
The method of claim 1 , wherein activating a field effect transistor comprises providing a high logic value to a gate of the field effect transistor.
Claim 10
Dependent Claim
30 words
The method of claim 1 , wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
Claim 11
Independent Claim
117 words
A method of accessing a memory cell using a memory cell access device, wherein the access device includes an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line, the method comprising: activating the n-channel field effect transistor for writing data to the memory cell; and activating an NPN bipolar junction transistor, coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 12
Independent Claim
117 words
A method of accessing a memory cell using a memory cell access device, wherein the access device includes an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line, the method comprising: activating the n-channel field effect transistor for writing data to the memory cell; and activating an NPN bipolar junction transistor, coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 13
Dependent Claim
25 words
The method of claim 10 , wherein activating afield effect transistor comprises providing a high logic value to a gate of the field effect transistor.
Claim 14
Dependent Claim
30 words
The method of claim 10 , wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
Claim 15
Independent Claim
71 words
A method of accessing a memory cell, the method comprising: activating a vertical pillar field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell; and activating a bipolar junction transistor coupled between the trench plate trench capacitor of the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 16
Independent Claim
71 words
A method of accessing a memory cell, the method comprising: activating a vertical pillar field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell; and activating a bipolar junction transistor coupled between the trench plate trench capacitor of the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 17
Dependent Claim
23 words
The method of claim 13 wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
Claim 18
Dependent Claim
21 words
The method of claim 14 wherein a body of the n-channel transistor is coupled to a base of the NPN transistor.
Claim 19
Dependent Claim
20 words
The method of claim 15 wherein a gate voltage of the field effect transistor varies between zero and three volts.
Claim 20
Dependent Claim
30 words
The method of claim 13 , wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
Claim 21
Independent Claim
119 words
A method of accessing a memory cell using a memory cell access device, wherein the access device includes a vertical pillar n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line, the method comprising: activating the n-channel field effect transistor for writing data to the memory cell; and activating an NPN bipolar junction transistor, coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 22
Independent Claim
119 words
A method of accessing a memory cell using a memory cell access device, wherein the access device includes a vertical pillar n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line, the method comprising: activating the n-channel field effect transistor for writing data to the memory cell; and activating an NPN bipolar junction transistor, coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 23
Dependent Claim
26 words
The method of claim 18 , wherein activating a field effect transistor comprises providing a high logic value to a gate of the field effect transistor.
Claim 24
Dependent Claim
30 words
The method of claim 18 , wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
Claim 25
Independent Claim
84 words
A method of accessing a memory cell, the method comprising: activating a field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell; and activating a bipolar junction transistor formed from a common structure with the field effect transistor, the bipolar junction transistor being coupled between the trench plate trench capacitor of the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 26
Independent Claim
84 words
A method of accessing a memory cell, the method comprising: activating a field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell; and activating a bipolar junction transistor formed from a common structure with the field effect transistor, the bipolar junction transistor being coupled between the trench plate trench capacitor of the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 27
Dependent Claim
23 words
The method of claim 21 wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
Claim 28
Dependent Claim
21 words
The method of claim 22 wherein a body of the n-channel transistor is coupled to a base of the NPN transistor.
Claim 29
Dependent Claim
20 words
The method of claim 23 wherein a gate voltage of the field effect transistor varies between zero and three volts.
Claim 30
Dependent Claim
30 words
The method of claim 21 , wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
Claim 31
Independent Claim
132 words
A method of accessing a memory cell using a memory cell access device, wherein the access device includes an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line, the method comprising: activating the n-channel field effect transistor for writing data to the memory cell; and activating an NPN bipolar junction transistor formed from a common structure with the field effect transistor, the bipolar junction transistor being coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 32
Independent Claim
132 words
A method of accessing a memory cell using a memory cell access device, wherein the access device includes an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line, the method comprising: activating the n-channel field effect transistor for writing data to the memory cell; and activating an NPN bipolar junction transistor formed from a common structure with the field effect transistor, the bipolar junction transistor being coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 33
Dependent Claim
25 words
The method of claim 26 wherein activating a field effect transistor comprises providing a high logic value to a gate of the field effect transistor.
Claim 34
Dependent Claim
29 words
The method of claim 26 wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
Claim 35
Independent Claim
117 words
A method of operating a memory device, comprising: accessing a signal from a memory cell, comprising: activating a field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell during a write operation; activating a bipolar junction transistor coupled between the trench plate trench capacitor of the memory cell and a data communication bit line for reading a charge stored on the memory cell during a read operation; transmitting the signal through the data communication bit line; and activating a sense amplifier to detect the signal transmitted to the data communication bit line by the bipolar junction transistor during the read operation.
Claim 36
Independent Claim
117 words
A method of operating a memory device, comprising: accessing a signal from a memory cell, comprising: activating a field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell during a write operation; activating a bipolar junction transistor coupled between the trench plate trench capacitor of the memory cell and a data communication bit line for reading a charge stored on the memory cell during a read operation; transmitting the signal through the data communication bit line; and activating a sense amplifier to detect the signal transmitted to the data communication bit line by the bipolar junction transistor during the read operation.
Claim 37
Dependent Claim
23 words
The method of claim 29 wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
Claim 38
Dependent Claim
21 words
The method of claim 30 wherein a body of the n-channel transistor is coupled to a base of the NPN transistor.
Claim 39
Dependent Claim
20 words
The method of claim 31 wherein a gate voltage of the field effect transistor varies between zero and three volts.
Claim 40
Dependent Claim
29 words
The method of claim 29 wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
Claim 41
Independent Claim
173 words
A method of operating a memory device, the memory device including a memory access device, wherein the access device includes a memory cell an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication bit line, the method comprising: accessing a signal from the memory cell, comprising: activating the n-channel field effect transistor for writing data to the memory cell during a write operation; activating an NPN bipolar junction transistor, coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell during a read operation, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication bit line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor; transmitting the signal through the data communication bit line; and activating a sense amplifier to detect the signal transmitted to the data communication bit line by the bipolar junction transistor during the read operation.
Claim 42
Independent Claim
173 words
A method of operating a memory device, the memory device including a memory access device, wherein the access device includes a memory cell an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication bit line, the method comprising: accessing a signal from the memory cell, comprising: activating the n-channel field effect transistor for writing data to the memory cell during a write operation; activating an NPN bipolar junction transistor, coupled in parallel with the n-channel field effect transistor, for reading a charge stored on the memory cell during a read operation, wherein the NPN bipolar junction transistor is coupled between the trench plate trench capacitor and the data communication bit line and wherein a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor; transmitting the signal through the data communication bit line; and activating a sense amplifier to detect the signal transmitted to the data communication bit line by the bipolar junction transistor during the read operation.
Claim 43
Dependent Claim
26 words
The method of claim 34 , wherein activating a field effect transistor comprises providing a high logic value to a gate of the field effect transistor.
Claim 44
Dependent Claim
30 words
The method of claim 34 , wherein activating a bipolar junction transistor comprises raising the voltage on a base of the bipolar junction transistor to forward bias a base-emitter junction.
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