US5821796A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuitry for providing a high impedance state when powering down a single port node
Assignee: Texas Instruments Inc
•
Filing: 1996-09-23
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Granted: 1998-10-13
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Expires: 2016-09-23
Abstract
Abstract A network circuit has a single port device 28 having a high impedance output node 42 when the single port device 28 is powered down; and a multi port device 50 having a bias node 60 coupled to the output node 42.
Inventors
- 👤 Dan Yaklin
- 👤 David K. Johnson
- 👤 Alan Wetzel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:01
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/028; H04L25/029; H03; H03K; H03K19/00; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
104 words
A driver circuit having a high impedance output node when powered down comprising: a first transistor having a drain, a gate, a source, and a back gate, the drain is coupled to the output node; a second transistor having a drain coupled to the back gate; a third transistor having a drain coupled to the back gate, a source coupled to a gate of the second transistor, and a gate coupled to a source of the second transistor; and a fourth transistor having a drain coupled to the gate of the second transistor and a gate coupled to the source of the second transistor.
Claim 2
Dependent Claim
104 words
A driver circuit having a high impedance output node when powered down comprising: a first transistor having a drain, a gate, a source, and a back gate, the drain is coupled to the output node; a second transistor having a drain coupled to the back gate; a third transistor having a drain coupled to the back gate, a source coupled to a gate of the second transistor, and a gate coupled to a source of the second transistor; and a fourth transistor having a drain coupled to the gate of the second transistor and a gate coupled to the source of the second transistor.
Claim 3
Dependent Claim
33 words
The circuit of claim 1 further comprising circuitry coupled to the gate to bias the gate to a potential on the output node to minimize current flow from the drain to the source.
Claim 4
Dependent Claim
31 words
The circuit of claim 2 wherein the circuitry coupled to the gate comprises a fifth transistor having a source coupled to the gate and a drain coupled to the output node.
Claim 5
Dependent Claim
21 words
The circuit of claim 1 wherein the driver circuit is in a single port device coupled to a multi port device.
Claim 6
Dependent Claim
23 words
The circuit of claim 1 wherein the output node is coupled to a bias node of a multi port device through a resistor.
Claim 7
Dependent Claim
103 words
A circuit for providing a high impedance output node when powered down comprising: a first MOSFET having a drain coupled to the output node; a second MOSFET having a drain coupled to the back gate; a third MOSFET having a drain coupled to the back gate, a source coupled to a gate of the second MOSFET, and a gate coupled to a source of the second MOSFET; a fourth MOSFET having a drain coupled to the gate of the second MOSFET and a gate coupled to the source of the second MOSFET; and a multi port network device coupled to the output node.
Claim 8
Dependent Claim
103 words
A circuit for providing a high impedance output node when powered down comprising: a first MOSFET having a drain coupled to the output node; a second MOSFET having a drain coupled to the back gate; a third MOSFET having a drain coupled to the back gate, a source coupled to a gate of the second MOSFET, and a gate coupled to a source of the second MOSFET; a fourth MOSFET having a drain coupled to the gate of the second MOSFET and a gate coupled to the source of the second MOSFET; and a multi port network device coupled to the output node.
Claim 9
Dependent Claim
14 words
The circuit of claim 6 wherein the first MOSFET is a P channel MOSFET.
Claim 10
Dependent Claim
14 words
The circuit of claim 6 wherein the second MOSFET is a P channel MOSFET.
Claim 11
Dependent Claim
14 words
The circuit of claim 6 wherein the third MOSFET is a P channel MOSFET.
Claim 12
Dependent Claim
14 words
The circuit of claim 6 wherein the fourth MOSFET is an N channel MOSFET.
References Cited (Backward Citations)
EP0480201A1
Cited
EP0498377A2
Cited
US5208492A
Cited
US5552723A
Cited
US5276364A
Cited
US5387826A
Cited
US5592510A
Cited
US5512844A
Cited
US5576635A
Cited
US5629634A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |