EP0480201A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Off-chip drivers
Assignee: International Business Machines Corp
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Filing: 1991-09-13
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Granted: —
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Expires: 2011-09-13
Abstract
Abstract A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor (12) and an N-channel pull down transistor (14) serially arranged between a first voltage source (Vdd) having a supply voltage of a given magnitude and ground with the common point between the transistors forming a output terminal (Vout) to which is connected a circuit (28) including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor (16) is connected between the output terminal (Vout) and the gate electrode of the pull up transistor (12). A first input terminal is coupled to the gate electrode of the pull up transistor (12) through a transmission gate including a first N-channel field effect transistor (24) arranged in parallel with a second P-channel field effect transistor (26), with a gate electrode of the first N-channel transistor (24) being connected to the first voltage source (Vdd) and the gate electrode of the second P-channel transistor (26) being connected to the output terminal (Vout).
Inventors
- 👤 John Stephen Austin
- 👤 Ronald Alan Piro
- 👤 Douglas Willard Stout
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 03:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
118 words
An off-chip driver circuit comprising a pull up transistor (12), an output terminal (Vout), voltage source means (Vdd) for providing a supply voltage of a given magnitude, said pull up transistor being disposed between said voltage source means and said output terminal, a control transistor (16) connected between a gate electrode of said pull up transistor and said output terminal having a gate electrode connected to a first point of reference potential (Vc), a transmission gate (22), a pre-driver circuit (10) coupled to the gate electrode of said pull up transistor through said transmission gate, and means (30) for selectively applying a voltage to said output terminal having a magnitude significantly greater than that of said given magnitude.
Claim 2
Dependent Claim
118 words
An off-chip driver circuit comprising a pull up transistor (12), an output terminal (Vout), voltage source means (Vdd) for providing a supply voltage of a given magnitude, said pull up transistor being disposed between said voltage source means and said output terminal, a control transistor (16) connected between a gate electrode of said pull up transistor and said output terminal having a gate electrode connected to a first point of reference potential (Vc), a transmission gate (22), a pre-driver circuit (10) coupled to the gate electrode of said pull up transistor through said transmission gate, and means (30) for selectively applying a voltage to said output terminal having a magnitude significantly greater than that of said given magnitude.
Claim 3
Dependent Claim
21 words
An off-chip driver circuit as set forth in claim 1 wherein said transmission gate includes a field effect transistor (24, 26).
Claim 4
Dependent Claim
34 words
An off-chip driver circuit as set forth in claim 2 wherein said field effect transistor is an N-channel field effect transistor (24) having a gate electrode connected to a second point of reference potential.
Claim 5
Dependent Claim
26 words
An off-chip driver circuit as set forth in any one of the preceding claims wherein said first point of reference potential is substantially said supply voltage.
Claim 6
Dependent Claim
28 words
An off-chip driver circuit as set forth in claim 3 or - if applicable - claim 4 wherein said second point of reference potential is said supply voltage.
Claim 7
Dependent Claim
35 words
An off-chip driver circuit as set forth in any one of the preceding claims further including a semiconductor substrate (32) supporting said transistors and means (18) for biasing said substrate coupled to said output terminal.
Claim 8
Dependent Claim
48 words
An off-chip driver circuit as set forth in claim 6 wherein said substrate includes a well - preferably an N-well - and said biasing means includes a well biasing transistor (18) - preferably a P-channel field effect transistor - having a gate electrode connected to said output terminal.
Claim 9
Dependent Claim
38 words
An off-chip driver circuit as set forth in any one of the preceding claims wherein said pull up transistor and said control transistor are P-channel field effect transistors and said transmission gate is an N-channel field effect transistor.
Claim 10
Dependent Claim
60 words
An off-chip driver circuit according to any one of the preceding claims further comprising a pull down transistor (14), said pull up transistor and said pull down transistor being serially connected between said voltage source means and a point of reference potential (ground), and said pre-driver circuit (10) being also coupled to a gate electrode of said pull down transistor.
Claim 11
Dependent Claim
36 words
An off-chip driver circuit as set forth in claim 9 wherein said pull up transistor and said control transistor are P-channel field effect transistors and said pull down transistor is a first N-channel field effect transistor.
Claim 12
Dependent Claim
35 words
An off-chip driver circuit according to any one of the preceding claims wherein said transmission gate includes a second N-channel field effect transistor (24) connected in parallel with a first P-channel field effect transistor (26).
Claim 13
Dependent Claim
42 words
An off-chip driver circuit as set forth in claim 11 wherein said second N-channel field effect transistor has a gate electrode connected to said supply voltage and said first P-channel field effect transistor has a gate electrode connected to said output terminal.
Claim 14
Dependent Claim
206 words
A CMOS driver comprising a first P-channel field effect transistor (12), a first N-channel field effect transistor (14), voltage source means (Vdd) for providing a supply voltage having a given magnitude, said first P-channel and said first N-channel transistors being serially connected between said voltage source means and a point of reference potential, an output terminal (Vout) connected to a common point between said first P-channel transistor and said first N-channel transistor, a second P-channel field effect transistor (16) connected between a gate electrode of said first P-channel transistor and said output terminal, first and second input terminals (IN', IN) said first input terminal (IN') being coupled to a gate electrode of said first N-channel transistor, a second N-channel field effect transistor (24) coupling said second input terminal (IN) to the gate electrode of said first P-channel transistor, gate electrodes of said second N-channel transistor and said second P-channel transistor being connected to points of fixed potential (Vdd, Vc), a third P-channel field effect transistor (26) connected in parallel with said second N-channel transistor having a gate electrode connected to said output terminal, and means (30) for selectively applying a voltage to said output terminal having a magnitude significantly greater than that of said given magnitude.
Claim 15
Dependent Claim
206 words
A CMOS driver comprising a first P-channel field effect transistor (12), a first N-channel field effect transistor (14), voltage source means (Vdd) for providing a supply voltage having a given magnitude, said first P-channel and said first N-channel transistors being serially connected between said voltage source means and a point of reference potential, an output terminal (Vout) connected to a common point between said first P-channel transistor and said first N-channel transistor, a second P-channel field effect transistor (16) connected between a gate electrode of said first P-channel transistor and said output terminal, first and second input terminals (IN', IN) said first input terminal (IN') being coupled to a gate electrode of said first N-channel transistor, a second N-channel field effect transistor (24) coupling said second input terminal (IN) to the gate electrode of said first P-channel transistor, gate electrodes of said second N-channel transistor and said second P-channel transistor being connected to points of fixed potential (Vdd, Vc), a third P-channel field effect transistor (26) connected in parallel with said second N-channel transistor having a gate electrode connected to said output terminal, and means (30) for selectively applying a voltage to said output terminal having a magnitude significantly greater than that of said given magnitude.
References Cited (Backward Citations)
EP0305676A2
Cited
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