Output buffer with improved tolerance to overvoltage

Claim 2

An output buffer, having a normal operation state and a high-impedance state, comprising: a pad, for providing and receiving a signal; a passgate, comprising a first transistor having a gate coupled to a first supply voltage and a second transistor coupled in parallel with said first transistor and having a gate coupled to a voltage bias node; a voltage bias generator, coupled to said voltage bias node, said voltage bias generator generates a first reference voltage when the output.buffer is in the normal operation state and a second reference voltage when the output buffer is in the high-impedance state; a pull-up transistor, having a source-to-drain path operatively coupling said first supply voltage to said pad, wherein said pull-up transistor provides a controlled variable impedance along said source-to-drain path in response to a control signal from a predriver coupled to a gate of said pull-up transistor through said passgate; a first tracking transistor, coupled between a gate of said pull-up transistor and said pad and having a gate coupled to said first supply voltage; a second tracking transistor, coupled between said pad and said voltage bias node and having a gate coupled to said first supply voltage; and a coupling capacitor, coupled between said pad and said voltage bias node.

Claim 3

The output buffer of claim 1 further comprising: a pull-down transistor, having a gate coupled to said predriver and having a drain-to-source path operatively coupling a second supply voltage to said pad.

Claim 4

The output buffer of claim 1 further comprising: a first pull-down transistor, having a gate coupled to said first supply and having a drain coupled to said pad; and a second pull-down transistor, having a gate coupled to said predriver and having a drain-to-source path operatively coupling a second supply voltage to said pad through a source of said first pull-down transistor.

Claim 5

The output buffer of claim 1 wherein said first reference voltage is about equal to a second supply voltage.

Claim 6

The output buffer of claim 1 wherein said second reference voltage is at least said first supply voltage less a transistor threshold voltage.

Claim 7

The output buffer of claim 1 wherein said second reference voltage is about equal to a pad voltage when said pad voltage is greater than said first supply voltage plus a transistor threshold voltage, and said second reference voltage is less than said first supply voltage less said transistor threshold voltage when said pad voltage is less than said first supply voltage plus said transistor threshold voltage.

Claim 8

The output buffer of claim 1 wherein said second reference voltage is about equal to a pad voltage when said pad voltage is greater than said first supply voltage plus a transistor threshold voltage, and said second reference voltage is about equal to said first supply voltage less said transistor threshold voltage when said pad voltage is less than said first supply voltage plus said transistor threshold voltage.

Claim 9

The output buffer of claim 1 wherein said voltage bias generator comprises: an inverter, having an input coupled to an output enable signal and having an output; and a passgate, comprising a third transistor having a gate coupled to said first supply voltage, said passgate couples said voltage bias node to said output of said inverter.

Claim 10

The output buffer of claim 1 wherein said coupling capacitor comprises: a PMOS transistor, having a gate coupled to said pad, and having a source and a drain coupled to said voltage bias node.

Claim 11

The output buffer of claim 1 wherein said coupling capacitor comprises: an NMOS transistor, having a gate coupled to said pad, and having a source and a drain coupled to said voltage bias node.

Claim 12

The output buffer of claim 1 wherein said pullup transistor is a PMOS transistor.

Claim 13

The output buffer of claim 1 wherein said first tracking transistor is a PMOS transistor.

Claim 14

The output buffer of claim 1 wherein said second tracking transistor is a PMOS transistor.

Claim 15

The output buffer of claim 11 wherein a well of said pull-up transistor is floating.

Claim 16

The output buffer of claim 11 wherein a well of said pull-up transistor is coupled to said pad through a parasitic diode.

Claim 17

The output buffer of claim 12 wherein a well of said first tracking transistor is floating.

Claim 18

The output buffer of claim 12 wherein a well of said first tracking transistor is coupled to said pad through a parasitic diode.

Claim 19

The output buffer of claim 13 wherein a well of said second tracking transistor is floating.

Claim 20

The output buffer of claim 13 wherein a well of said second tracking transistor is coupled to said pad through a parasitic diode.

Claim 21

The output buffer of claim 1 wherein said pullup transistor, first tracking transistor, second tracking transistor, and second transistor are PMOS transistors, and wherein each of said pull-up transistor, first tracking transistor, second tracking transistor, and second transistor has a floating well.

Claim 22

The output buffer of claim 1 wherein said pullup transistor, first tracking transistor, second tracking transistor, and second transistor are PMOS transistors, and wherein each of said pull-up transistor, first tracking transistor, second tracking transistor, and second transistor has a well coupled to said pad through a parasitic diode.

Claim 23

The output buffer of claim 2 wherein said first transistor and pull-down transistor are NMOS transistors.

Claim 24

The output buffer of claim 3 wherein said first transistor, first pull-down transistor, and second pull-down transistor are NMOS transistors.

Claim 25

The output buffer of claim 1 wherein said predriver comprises a buffer, wherein in the normal operation state, said buffer provides an output in response to an internal data signal representing a boolean logic state, and wherein in the high-impedance state, said buffer provides a high logic state.

Claim 26

The output buffer of claim 2 wherein said predriver comprises a buffer, wherein in the normal operation state, said buffer provides an output in response to an internal data signal representing a boolean logic state, and wherein in the high-impedance state, said buffer provides a high logic state to said pull-up transistor and a low logic state to said pull-down transistor.

Claim 27

The output buffer of claim 1 further comprising a third transistor in parallel with said first transistor and having a gate coupled to said pad.

Claim 28

The output buffer of claim 1 further comprising: a substrate bias generator having an output coupled to a well of said pull-up transistor, comprising: a first PMOS bias transistor, coupled between said first supply voltage and said output of said substrate bias generator, wherein a gate of said first PMOS bias transistor is coupled to said pad, wherein a well of said first PMOS bias transistor is coupled to said output of said substrate bias generator; and a second PMOS bias transistor, coupled between said output of said substrate bias generator and said pad, wherein a gate of said second PMOS bias transistor is coupled to said first supply voltage, wherein a well of said second PMOS bias transistor is coupled to said output of said substrate bias generator.

Claim 29

The output buffer of claim 1 further comprising: a substrate bias generator having an output coupled to a well of said second tracking transistor, comprising: a first PMOS bias transistor, coupled between said first supply voltage and said output of said substrate bias generator, wherein a gate of said first PMOS bias transistor is coupled to said pad, wherein a well of said first PMOS bias transistor is coupled to said output of said substrate bias generator; and a second PMOS bias transistor, coupled between said output of said substrate bias generator and said pad, wherein a gate of said second PMOS bias transistor is coupled to said first supply voltage, wherein a well of said second PMOS bias transistor is coupled to said output of said substrate bias generator.

Claim 30

The output buffer of claim 1 further comprising: a substrate bias generator having an output coupled to a well of said first tracking transistor, comprising: a first PMOS bias transistor, coupled between said first supply voltage and said output of said substrate bias generator, wherein a gate of said first PMOS bias transistor is coupled to said pad, wherein a well of said first PMOS bias transistor is coupled to said output of said substrate bias generator; and a second PMOS bias transistor, coupled between said output of said substrate bias generator and said pad, wherein a gate of said second PMOS bias transistor is coupled to said first supply voltage, wherein a well of said second PMOS bias transistor is coupled to said output of said substrate bias generator.

Claim 31

An output buffer, having a normal operation state and a high-impedance state, comprising: a pad, for providing and receiving a signal; a passgate, comprising a first transistor having a gate coupled to a first supply voltage and a second transistor coupled in parallel with said first transistor and having a gate coupled to a voltage bias node; a voltage bias generator, coupled to said voltage bias node, said voltage bias generator generates a first reference voltage when the output buffer is in the normal operation state and a second reference voltage when the output buffer is in the high-impedance state, wherein said first reference voltage is about equal to a second supply voltage, wherein said second reference voltage is about equal to a pad voltage when said pad voltage is greater than said first supply voltage plus a transistor threshold voltage and said second reference voltage is about equal to said first supply voltage less said transistor threshold voltage when said pad voltage is less than said first supply voltage plus said transistor threshold voltage; a pull-up transistor, having a source-to-drain path operatively coupling said first supply voltage to said pad, wherein said pull-up transistor provides a controlled variable impedance along said source-to-drain path in response to a control signal from a predriver coupled to a gate of said pull-up transistor through said passgate; a pull-down transistor, having a gate coupled to said predriver and having a drain-to-source path operatively coupling said second supply voltage to said pad; a first tracking transistor, coupled between a gate of said pull-up transistor and said pad and having a gate coupled to said first supply voltage; a second tracking transistor, coupled between said pad and said voltage bias node and having a gate coupled to said first supply voltage; and a coupling capacitor, coupled between said pad and said voltage bias node.

Claim 32

An output buffer, having a normal operation state and a high-impedance state, comprising: a pad, for providing and receiving a signal; a passgate, comprising a first transistor having a gate coupled to a first supply voltage and a second transistor coupled in parallel with said first transistor and having a gate coupled to a voltage bias node; a voltage bias generator, coupled to said voltage bias node, said voltage bias generator generates a first reference voltage when the output buffer is in the normal operation state and a second reference voltage when the output buffer is in the high-impedance state, wherein said first reference voltage is about equal to a second supply voltage, wherein said second reference voltage is about equal to a pad voltage when said pad voltage is greater than said first supply voltage plus a transistor threshold voltage and said second reference voltage is about equal to said first supply voltage less said transistor threshold voltage when said pad voltage is less than said first supply voltage plus said transistor threshold voltage; a pull-up transistor, having a source-to-drain path operatively coupling said first supply voltage to said pad, wherein said pull-up transistor provides a controlled variable impedance along said source-to-drain path in response to a control signal from a predriver coupled to a gate of said pull-up transistor through said passgate; a pull-down transistor, having a gate coupled to said predriver and having a drain-to-source path operatively coupling said second supply voltage to said pad; a first tracking transistor, coupled between a gate of said pull-up transistor and said pad and having a gate coupled to said first supply voltage; a second tracking transistor, coupled between said pad and said voltage bias node and having a gate coupled to said first supply voltage; and a coupling capacitor, coupled between said pad and said voltage bias node.

Claim 33

A floating-well MOS output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a first transistor, coupled between the pad and a control node of said pull-up driver; a second transistor, coupled between said pad and a voltage bias node; and a voltage bias generator for generating a signal at said voltage bias node.

Claim 34

A floating-well MOS output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a first transistor, coupled between the pad and a control node of said pull-up driver; a second transistor, coupled between said pad and a voltage bias node; and a voltage bias generator for generating a signal at said voltage bias node.

Claim 35

The floating-well MOS output buffer of claim 31 further comprising: a capacitor coupled between the pad and said voltage bias node.

Claim 36

The floating-well MOS output buffer of claim 31 further comprising: a passgate coupled to transfer a control signal to said control node, said passgate comprising a third transistor having a control node coupled to said voltage bias node.

Claim 37

The floating-well MOS output buffer of claim 31 wherein said voltage bias generator generates a first reference voltaqe when the output buffer is in a normal operation state and a second reference voltage when the output buffer is in a high-impedance state.

Claim 38

A floating-well MOS output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a predriver, coupled to a control node of said pull-up driver, said first supply voltage, and said second supply voltage, for driving said pull-up driver; and a first transistor, coupled between said predriver and said control node of said pull-up driver, and having a gate coupled to a voltage bias node; a second transistor coupled between the pad and said voltage bias node, wherein said second transistor decouples the pad from said gate of said first transistor.

Claim 39

A floating-well MOS output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a predriver, coupled to a control node of said pull-up driver, said first supply voltage, and said second supply voltage, for driving said pull-up driver; and a first transistor, coupled between said predriver and said control node of said pull-up driver, and having a gate coupled to a voltage bias node; a second transistor coupled between the pad and said voltage bias node, wherein said second transistor decouples the pad from said gate of said first transistor.

Claim 40

A floating-well MOS output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a predriver for controlling said pull-up driver; a first transistor coupling said predriver to a control node of said pull-up driver, and having a gate coupled to a voltage bias node; a coupling capacitor coupled between the .pad and said voltage bias node.

Claim 41

A floating-well MOS output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a predriver for controlling said pull-up driver; a first transistor coupling said predriver to a control node of said pull-up driver, and having a gate coupled to a voltage bias node; a coupling capacitor coupled between the .pad and said voltage bias node.

Claim 42

A floating-well M0S output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a first transistor, coupled between the pad and a control node of said pull-up driver; a second transistor, coupled between said pad and a voltage bias node; and a third transistor, coupled between a predriver and said control node of said pull-up driver, and having a gate coupled to a voltage bias node.

Claim 43

A floating-well M0S output buffer for producing a signal on a pad of an integrated circuit comprising: a pull-up driver, coupled to the pad and a first supply voltage, for connecting said first supply voltage to the pad; a pull-down driver, coupled to the pad and a second supply voltage, for connecting said second supply voltage to the pad; a first transistor, coupled between the pad and a control node of said pull-up driver; a second transistor, coupled between said pad and a voltage bias node; and a third transistor, coupled between a predriver and said control node of said pull-up driver, and having a gate coupled to a voltage bias node.