Floating-well CMOS output driver

Claim 1

A floating well CMOS output driver comprising: a. a pull-up transistor having a source-to-drain path and a gate, the source-to-drain path connected at a first end to a supply terminal and connected at a second end to an output terminal; b. a pull-down transistor having a source-to-drain path and a gate, the source-to-drain path of the pull-down transistor connected at a first end to ground, the gate of the pull-down transistor connected to a negative logic input; c. a cascode transistor having a source-to-drain path and a gate, the source-to-drain path connected in series between the second end of the pull-up transistor and the second end of the pull-down transistor, the gate of the cascode transistor connected to the supply terminal; d. a floating well circuit comprising i. first and second transistors each having a source-to-drain path and a gate, the source-to-drain paths of the first and second transistors being each connected at a first end to the supply terminal, a second end of the source-to-drain paths of the first and second transistors, the gate of the first transistor, and the wells of the first and second transistors each being connected to a floating well circuit output node coupled to the well of the pull-up transistor; and ii. third and fourth transistors each having a source-to-drain path and a gate, a first end of the source-to-drain path of each of the third and fourth transistors connected to the output terminal, a second end of the source-to-drain path of each of the third and fourth transistors and the gate of the fourth transistor each connected to the floating well circuit output node, the gate of the third transistor connected to the supply terminal; and e. a floating gate circuit comprising i. fifth and sixth transistors each having a source-to-drain path and a gate, the source-to-drain paths of the fifth and sixth transistors each connected at one end to a positive logic input, the other end of the source-to-drain paths of the fifth and sixth transistors connected to a floating gate circuit output node which is connected to the gate of the pull-up transistor, the gate of the fifth transistor connected to the supply terminal, the gate of the sixth transistor connected to the output terminal, and the well of the sixth transistor connected to the floating well circuit output node; and ii. an seventh transistor having a source-to-drain path and a gate, a first end of the source-to-drain path of the seventh transistor connected to the output terminal, a second end of the source-to-drain path of the seventh transistor connected to the floating gate circuit output node, the gate of the seventh transistor connected to the supply terminal, and the well of the sixth transistor connected to the floating well circuit output node.